powerpc 处理器上的外部中断是如何引导的？
也许问题应该是，外部中断是否在 PowerPC 上进行了向量化？我一直在查看 http://www.ibm。 com/developerworks/eserver/library/es-archguide-v2.html，“book 3”，试图弄清楚处理器如何定位适当的中断服务例程以响应外部中断。这似乎表明，当PPC识别出外部中断时，它只是将执行跳转到0x0000_0500。
我可能对 PPC 的运作方式存在误解。在 x86 中，处理器通过中断确认周期响应中断请求，并直接从设备获取“向量”。然后，该向量（实际上是一个索引）允许 CPU 从其中断向量表中选择适当的处理程序例程。最重要的是，这种确认/向量获取是硬件、总线协议的事情，没有人需要编写任何代码来实现它。唯一需要写入（读取、软件）的代码是 ISR 本身。
PPC 是否会做类似的事情？ 0x500处会有向量表吗？或者它是否做了一些完全不同的事情，并将获取设备向量的功能卸载到外部中断控制器？我想它可以只是跳转到0x500处的代码，然后实际软件将询问（假设的？）中断控制器以获取向量..然后在跳转表/什么中使用它-你，但我找不到文档来验证情况是否如此，无论怎样。
Maybe the question should be, are external interrupts even vectored on the PowerPC at all? I've been looking at http://www.ibm.com/developerworks/eserver/library/es-archguide-v2.html, 'book 3', trying to figure out how the processor locates the appropriate interrupt service routine in response to an external interrupt. It seems to suggest that when the PPC recognizes an external interrupt, it just jumps execution to 0x0000_0500.
I may be laboring under a misconception about how the PPC works. With x86, the processor responds to interrupt requests with an interrupt acknowledge cycle, and obtains a 'vector' directly from the device. The vector (really an index) then allows the cpu to pick an appropriate handler routine from its interrupt vector table. Most importantly, this acknowledge/vector fetch is a hardware, bus-protocol thing, nobody has to write any code to make it happen. The only code that needs writing (read, software) is the ISRs themselves.
Does the PPC do something similar? Would there be a table of vectors at 0x500? Or does it do something radically different, and offload the functionality of getting the device's vector to an external interrupt controller? I suppose it could just jump to code at 0x500, where actual software would then interrogate the (hypothetical?) interrupt controller to get the vector .. and then use it in a jump-table/what-have-you, but I can't find documentation to verify this is the case, one way or another.
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PowerPC CPU没有中断向量表的概念，只提供单个中断引脚和中断向量。
The PowerPC CPU has no concept of an interrupt vector table, and only provides a single interrupt pin and interrupt vector.