如何在设备驱动程序及其控制的 FPGA 之间共享寄存器和位字段定义
是否有任何好的现有软件工具可以帮助生成 C 头文件，其中包含适当的寄存器偏移#defines 以及 VHDL 的位定义？如果确实存在此类工具，它们对 VHDL 有哪些限制以及应如何指定应导出的内容？
到目前为止，我已经找到了这些工具，但它们并不完全是我正在寻找的：
- Vregs 由 Veripool
- SpectraReg 由 PDTi
- Bitwise by Duolog
基于这些工具，我也感兴趣是否正确的工作流程是生成 C 和 VHDL，而不是尝试直接从VHDL（可能在注释中有额外的标签）到 C.
Are there any good, existing software tools available to assist in generating C header files with appropriate #defines for register offsets as well as bit definitions from VHDL? If any such tools do exist, what restrictions to they place on the VHDL and how are things that should be exported designated?
So far, I've found these tools but they aren't exactly what I'm looking for:
- Vregs by Veripool
- SpectraReg by PDTi
- Bitwise by Duolog
Based upon these tools I am also interested if the proper workflow is to generate both the C and the VHDL rather than trying to go directly from VHDL (perhaps with extra tags in the comments) to C.
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你可以看看 doxygen，它支持 VHDL 语言，通过使用中间文件，你可以或多或少容易地提取信息。副产品将是您的 RTL 代码文档。
另一种选择是根据 Yacc/Lex 定义构建 C 解析器，您可以找到几个 此处。从那里，您可以解析 VHDL、提取信息（您必须确定如何检索寄存器的定义）并生成 C 头文件。这可能相当复杂。
但如果我是你，我真的会采取不同的方式，在一个单独的文件中（例如，在 XML 中）定义寄存器偏移量和字段，并编写一个小脚本来生成 C 头文件和 VHDL 包，这将为你节省大量的时间，并且从流程的角度来看会更加稳健。
这也将有助于构建任何文档。
当然，您可以使用 makefile/或在模拟/综合之前准备数据库的脚本中自动化该过程。
You could have a look at doxygen, it supports the VHDL language and by using intermediate files you may be able to extract the information more or less easily. A by-product would be your RTL code documentation.
Another option is to build a C parser from the Yacc/Lex definitions, you can find several ones here. From there, you can parse the VHDL, extract the information (you will have to determine how to retrieve the definition of your registers) and produce a C header file. It's probably quite complicated.
But if I were you, I would really proceed differently and define the register offsets and fields in a separate file (for example, in XML), and write a small script to generate both C headers and a VHDL package, this would save you a lot of time and would be more robust from a flow point of view.
That would also help in building any documentation.
You could of course automate the process with a makefile/or in a script that prepares the database before simulation/synthesis.
我同意 Marty 的观点，创建内部脚本来完成这类事情很有趣，但从长远来看可能会出现问题。
我们创建了一个名为 IDesignSpec 的工具，它作为文档编辑器的插件实现，使您能够在文档中指定寄存器并生成 C 标头、VHDL、Verilog、OVM、VMM、IP-XACT、HTML、XML、SystemRDL、PDF 等。从它。
您可以使用 TCL API 生成自定义输出。它也可以读取各种输入格式，例如 XML、IP-XACT、SystemRDL 等。
这种方法的好处是您拥有一个规范，并且所有内容都会自动保持同步。
目前支持的编辑器有：MS Word 2003 和 MS Word 2003。 2007 年，OpenOffice、StarOffice 和 FrameMaker。
您可以访问 http://www.agnisys.com 获取更多详细信息
以下是可用解决方案的完整列表：
公司名称：商业工具（提供解决方案）
免费/开源工具
I agree with Marty, creating in-house scripts to do this sort of thing is fun but can be problematic in the long run.
We have created a tool called IDesignSpec which is implemented as a Plugin for document editors that enable you to specify registers in a document and generate C header, VHDL, Verilog, OVM, VMM, IP-XACT, HTML, XML, SystemRDL, PDF etc. from it.
You can generate custom outputs using the TCL API. It can read in various input formats as well such as XML, IP-XACT, SystemRDL, etc.
The benefit of this approach is that your you have one specification and everything automatically keeps in sync.
Currently supported editors are : MS Word 2003 & 2007, OpenOffice, StarOffice and FrameMaker.
You can get more details at http://www.agnisys.com
Here is the complete list of solutions available:
Company name : Commercial tools (solution provided)
Free/OpenSource tools
我认为虽然这一直困扰着你，但最终却让你朝着正确的方向前进。我同意 RedGlyph 的观点，你应该考虑稍微改变一下你的工作流程。
您是否考虑过为您的控制寄存器信息创建一个“主文档”，并由此自动生成所有内容 - RTL、测试台代码、驱动程序软件标头和文档？
我曾经参与过一些项目，其中控制信息保存在一个主电子表格中，我们需要的一切都从中生成。在一个芯片系列上，我编写了一些 Python 脚本来从电子表格导出的 CSV 文件生成这些内容。在另一个项目中，电子表格包含用于生成我们需要的 RTL 文件等的宏。
编写内部脚本很好，因为您可以完全控制它们并了解它们的详细工作原理。但请记住，您必须花时间支持这些脚本并更新它们以执行新操作。并考虑一下，如果编写这些脚本的人决定去找一份新工作，会发生什么 - 其他人是否足够熟悉这些脚本来修改它们？出于上述原因，我们正在考虑购买第三方工具。
我还参与过从 RTL 向后移植文档和头文件的项目 - 这是一场噩梦。文档通常落后于设计，并且控制字段常常会“丢失”。我宁愿不再参与这样的项目；）
I think that final though that was bugging you is sending you in the right direction. And I'd agree with RedGlyph in that you should consider changing your work flow a little.
Have you thought about having one 'master document' for your control register information and generated everything automatically from this - RTL, testbench code, driver software headers and documentation?
I've worked on projects where the control info was kept in one master spreadsheet and everything we needed generated from this. On one family of chips, I'd written a few Python scripts to generate this stuff from CSV files exported from the spreadsheet. On another project, the spreadsheet contained macros to generate the RTL files etc that we needed.
Writing in-house scripts is all fine and good as you've total control over them and know how they work in detail. But remember that you have to spend time supporting these scripts and updating them to do new things. And consider what would happen if whoever wrote these scripts decided to go get a new job - would anyone else be familiar enough with the scripts to modify them? We're considering buying in a 3rd party tool for the reasons mentioned above.
I've also worked on projects were the documentation and header files was back-ported from the RTL -it was a nightmare. Documentation usually lagged behind the design, and often control fields would 'go missing'. I'd rather not be involved in such a project again ;)
我们的设计小组使用 SystemRDL 来捕获我们的可编程片上系统的寄存器定义。我们使用 Denali Blueprint 以及针对各种目标的定制脚本 - 生成寄存器映射、PDF 文档、验证、C 头文件等。
我们还没有使用它来生成 RTL 源代码。
http://www.spiritconsortium.org/releases/SystemRDL
http://www.google.com/search?q=SystemRDL
Our design group uses SystemRDL to capture the register definitions for our Programmable System-on-Chip. We use Denali Blueprint with customized scripts for the various targets - generate the register map, PDF documentation, Verification, C header files, etc.
We are not using it to generate the RTL source yet.
http://www.spiritconsortium.org/releases/SystemRDL
http://www.google.com/search?q=SystemRDL
答案可能来得有点晚，但我们使用免费的 netpp 库和一些修改过的 XSL 样式表从一个 XML 源生成文档、VHDL 和 C 源代码。
还有一个 VHDL 模拟器扩展，可让 VHDL 和 C 库交换数据以创建具有联网功能的“虚拟 FPGA”。它叫做 ghdlex，我不太记得它在哪里，但你会在 http://section5.ch网站下的netpp下载区。使用起来有点棘手，但好在，它是免费的..
The answer might come a bit late, but we use the free netpp library and some modified XSL style sheets to generate documentation, VHDL and C source from one XML source.
There's also a VHDL simulator extension that lets VHDL and C libraries exchange data to create a networking capable 'virtual FPGA'. It's called ghdlex, I don't exactly recall where it is, but you will find it somewhere on the http://section5.ch website under the netpp download area. It's a bit tricky to use, but well, it's free..
共享信息的真正来源是您的原始设计，因此我会以易于处理的形式输入原始设计。这里有一些想法...
使用 YAML。（或者，叹息，XML，甚至是您设计的非常简单的 DSL。）定义原始数据。编写脚本将其转储为 VHDL 和 C。所有脚本语言都支持 YAML，并且它也设计为可以使用 shell 工具进行解析。您甚至可以使用简化的 VHDL 或 C，并编写一个脚本，通过简单的文本转换将其转换为相应的 C 或 VHDL。
这一切都在 C 预处理器中完成。您可以编写一组指定寄存器布局的宏调用。然后，您可以拥有一个
#if或两个单独的.h文件来定义定义宏的两个不同版本，一个扩展为 VHDL，另一个扩展为相同的定义The real source of the shared information is your original design, so I would enter the original design in a form that is easy to process. Here are a couple of ideas...
Use YAML. (Or, sigh, XML, or even a very simple DSL of your design.) Define the original data. Write scripts to dump it as VHDL and C. All the scripting languages support YAML and it's designed to be parsed with shell tools as well. You might even use simplified VHDL or C, and write a script to turn that via a simple text transformation into the corresponding C or VHDL.
Do it all in the C preprocessor. You could write a set of macro calls that specify register layouts. You could then have a
#ifor perhaps two separate.hfiles that define two different versions of your definition macros, one which expands into VHDL and one which expands those same definitions into C.Spectareg 允许您在一处指定寄存器并为不同环境创建多个输出（例如 VHDL、C、Verilog）
Spectareg allows you to specify the registers in one place and create multiple outputs for different environments (eg. VHDL, C, Verilog)