在gnu make中，静态模式规则中的先决条件可以有不同的后缀吗

发布于 2024-08-08 07:23:30 字数 318 浏览 3 评论 0原文

我们的 make 文件使用如下静态模式规则编译 .c 源文件：

OBJECTS = foo.o bar.o baz.o

$(OBJECTS): %.o: %.c
    $(CC) $< $(C_OPTIONS) -c -o $@

我需要将其中一个 .c 文件更改为 Objective-C .m 文件。对于两种源类型，调用编译器是相同的，因此我想使用相同的规则，只是调整它以使其更加灵活。我不想更改 OPTIONS 变量，因为它也用于链接步骤等。

有没有办法使上面的规则更灵活以适应 .c 和 .m 文件？

谢谢

原文

Our make file compiles .c source files with a static pattern rule like this:

OBJECTS = foo.o bar.o baz.o

$(OBJECTS): %.o: %.c
    $(CC) lt; $(C_OPTIONS) -c -o $@

I need to change one of the .c files to an Objective-C .m file. Invoking the compiler is the same for both source types, so I'd like to use the same rule and just tweak it to be more flexible. I'd rather not change the OPTIONS variable because it's also used for the linking step, etc.

Is there a way to make the rule above more flexible to accommodate both .c and .m files?

Thanks

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自此以后，行同陌路 2024-08-15 07:23:30

我们可以将这种非此即彼的行为添加到 Make 应该能够轻松完成但实际上却做不到的事情列表中。这是一种方法，使用“eval”为每个对象创建单独的规则。

define RULE_template
$(1): $(wildcard $(basename $(1)).[cm])
endef

OBJECTS = foo.o bar.o baz.o

$(foreach obj,$(OBJECTS),$(eval $(call RULE_template,$(obj))))

$(OBJECTS):
    $(CC) lt; $(C_OPTIONS) -c -o $@

请注意，这取决于运行 Make 之前已存在的源文件（foo.c 或 foo.m，但不是两者）。如果您在同一步骤中生成这些源，则这将不起作用。

这是一个不太聪明、更稳健的方法。

CPP_OBJECTS = foo.o bar.o
OBJECTIVE_OBJECTS = baz.o
OBJECTS = $(CPP_OBJECTS) $(OBJECTIVE_OBJECTS)

$(CPP_OBJECTS): %.o: %.c 

$(OBJECTIVE_OBJECTS): %.o: %.m 

$(OBJECTS):
    $(CC) lt; $(C_OPTIONS) -c -o $@

编辑：更正了对象分配，感谢 Jonathan Leffler。

We can add this either-or behavior to the list of things Make should be able to do easily, but isn't. Here's a way to do it, using "eval" to create a seperate rule for each object.

define RULE_template
$(1): $(wildcard $(basename $(1)).[cm])
endef

OBJECTS = foo.o bar.o baz.o

$(foreach obj,$(OBJECTS),$(eval $(call RULE_template,$(obj))))

$(OBJECTS):
    $(CC) lt $(C_OPTIONS) -c -o $@

Note that this depends on the source files already existing before you run Make (foo.c or foo.m, but not both). If you're generating those sources in the same step, this won't work.

Here's a less clever, more robust method.

CPP_OBJECTS = foo.o bar.o
OBJECTIVE_OBJECTS = baz.o
OBJECTS = $(CPP_OBJECTS) $(OBJECTIVE_OBJECTS)

$(CPP_OBJECTS): %.o: %.c 

$(OBJECTIVE_OBJECTS): %.o: %.m 

$(OBJECTS):
    $(CC) lt $(C_OPTIONS) -c -o $@

EDIT: corrected OBJECTS assignment, thanks to Jonathan Leffler.

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好久不见√ 2024-08-15 07:23:30

并不是真的只是复制到

$(OBJECTS): %.o: %.m
  $(CC) lt; $(C_OPTIONS) -c -o $@

Not really just copy to

$(OBJECTS): %.o: %.m
  $(CC) lt; $(C_OPTIONS) -c -o $@

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甜宝宝 2024-08-15 07:23:30

对同一个编译器的调用只是一个愉快的场合。通常，您不会使用 $(CC) 编译 Objective-C 代码。这感觉很奇怪。

但既然你采取了严厉的方式，我不会发布正确的解决方案，在该解决方案中，你将 Objective-C 目标与 C 目标分离成两个不同的 $(OBJECTS) 类变量，然后使两条规则（你确实应该这样做）。太无聊了。相反，采取黑客行动！

OBJC_FILES:=$(subst $(wildcard *.m))

real_name = `(test -h $(1) && readlink $(1) ) || echo $(1)`

$(OBJECTS): %.o: %.c
  $(GCC) lt; $(C_OPTIONS) -c -o $(call real_name,$@)

$(OBJC_FILES): %.c: %.m
  ln -s lt; $@

愿上帝帮助那些维护它的人！

顺便说一句，如果您生成了 m 文件，这显然不起作用。

The call to the same compiler is just a happy occasion. Normally you do not compile objective-c code with $(CC). That just feels strange.

But since you go in a harsh way, I won't post do-it-right solution, where you separate objective-C targets from C targets into two different $(OBJECTS)-like variables and make two rules (which you should really do). Too boring. Instead, take a hack!

OBJC_FILES:=$(subst $(wildcard *.m))

real_name = `(test -h $(1) && readlink $(1) ) || echo $(1)`

$(OBJECTS): %.o: %.c
  $(GCC) lt; $(C_OPTIONS) -c -o $(call real_name,$@)

$(OBJC_FILES): %.c: %.m
  ln -s lt; $@

And God help those who maintains it!

Btw, this obviously won't work if your m-files are generated.

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