如何处理makefile中的环境设置?

发布于 2024-08-07 02:19:55 字数 376 浏览 1 评论 0原文

因此,要编译我的可执行文件,我需要正确设置库位置。问题是,设置来自一堆执行环境变量导出的脚本,并且需要设置的内容可能会发生变化(超出我的控制范围),因此我需要使用这些脚本而不是复制它们的功能。要在常规命令行中进行编译,我需要执行以下操作:

setup library1
setup library2
source some_other_setup_script.bash
g++ blah.c
# setup is a executable on my system that run some scripts

我将如何编写一个 makefile 来完成此任务?据我尝试,环境变量导出不会延续(即“export VAR=remember; echo $VAR”不起作用)

So, to compile my executable, I need to have the library locations set up correctly. The problem is, the setup comes from a bunch of scripts that do the env variable exporting, and what needs to be set up may change (beyond my control) so I need to use those scripts instead of copying their functionality. To compile in regular command line, I need to do something like:

setup library1
setup library2
source some_other_setup_script.bash
g++ blah.c
# setup is a executable on my system that run some scripts

How would I write a makefile that accomplishes that? As far as I tried, the env variable exporting does not carry over (i.e. "export VAR=remember; echo $VAR" won't work)

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此刻的回忆 2024-08-14 02:19:55

您还可以使用 GNU make 的机制正确添加环境变量,如下所示:

export TEST:="Something Good!"
test:
    echo $TEST

这(我认为)与以下内容具有不同的语义:

TEST2:="Something not quite so useful?"
test2:
    echo ${TEST2}

Which(我再次认为)在传递到 shell 之前在 make 中进行替换。请注意,导出命令在目标块中不起作用,只是未缩进为立即执行的命令。

You can also add environment variables properly with the machinery of GNU make, like so:

export TEST:="Something Good!"
test:
    echo $TEST

This (I think) has different semantics from:

TEST2:="Something not quite so useful?"
test2:
    echo ${TEST2}

Which (again, I think) does the substitution within make before passing along to the shell. Note that the export command doesn't work within a target block, just unindented as an immediately executed command.

泪冰清 2024-08-14 02:19:55

如果变量导出不像在命令行上那样工作,则表明 Make 正在选择与您正在使用的 shell 不同的 shell,并使用不同的语法来处理变量 (export VAR=remember; echo $VAR 对我来说效果很好)。 Make 默认使用 /bin/sh,但您可以使用 SHELL 变量覆盖它,Make 不会从环境中导入该变量。我建议将 SHELL(在 Makefile 中)设置为您在环境中使用的任何内容,然后再次尝试 export VAR=remember 实验。

If variable exporting is not working the way it does on your command line, that suggests that Make is choosing a shell different from the one you're using, with different syntax for handling variables (export VAR=remember; echo $VAR works fine for me). Make uses /bin/sh by default, but you can override this with the SHELL variable, which Make does not import from the environment. I suggest setting SHELL (in the Makefile) to whatever you're using in your environment and trying the export VAR=remember experiment again.

雪若未夕 2024-08-14 02:19:55

最终,您需要定义变量并在 shell 列表甚至脚本中执行编译器,而不是在单独的 make 命令中。不过,您可以添加一些改进。您可以告诉 make 有关脚本的信息:

maintarget: script.sh blah.c
    source script.sh; g++ blah.c

script.sh:
    setup include script here

另一件事是在同一个 shell 中执行所有这些内容,

maintarget: blah.c
    run this; run that; run the other thing; g++ blah.c 

我相信所有 make 版本都会运行 ; list 在同一个 shell 中,但您始终可以使用 (list) 强制使用子 shell,或者通过专门调用 shell 脚本作为编译器命令包装器。

不要忘记适当的目标取决于您的脚本本身。顺便说一句,某些 make 版本(pmake 又名 bsd make)可以在定义 make 变量时执行命令,并且所有版本的 make 然后导出它们。但我不认为 gmake 能做到这一点。

Ultimately you will need to define the variable and execute the compiler in a shell list or even a script, rather than in separate make commands. There are a couple of refinements you could add, however. You could tell make about the script:

maintarget: script.sh blah.c
    source script.sh; g++ blah.c

script.sh:
    setup include script here

Another thing would be to just execute all that stuff in the same shell

maintarget: blah.c
    run this; run that; run the other thing; g++ blah.c 

I believe all make versions will run a ; list in the same shell, but you can always force a subshell with (list) or by calling specifically a shell script as a compiler command wrapper.

Don't forget to have the appropriate targets depend on your scripts themselves. BTW, some make versions (pmake aka bsd make) can execute a command when defining a make variable, and all versions of make then exports those. But I don't think gmake can do that.

青柠芒果 2024-08-14 02:19:55

您可以编写另一个 shell 脚本来执行所有这些命令,然后打印出 make 可以使用的变量分配。运行脚本,将其输出通过管道传输到文件,然后从 Makefile 中包含该文件。例如:

Makefile:

all:
    echo $(FOO)

test.mk: test.sh
    ./
lt; > $@

include test.mk

test.sh

echo "FOO=1"

在包含此 Makefile 的目录中运行“make”会生成:

make: Entering directory `/home/luser/build/mktest'
Makefile:7: test.mk: No such file or directory
./test.sh > test.mk
make: Leaving directory `/home/luser/build/mktest'
make: Entering directory `/home/luser/build/mktest'
echo 1
1
make: Leaving directory `/home/luser/build/mktest'

make 通过运行 shell 脚本创建 test.mk,然后包含它。 test.mk 包含 test.sh 的输出,并被解析为 Makefile。请参阅 http://www.gnu.org/software/make/manual /make.html#Ininclude 了解更多详细信息。

我们在 Mozilla 的 client.mk 中使用此变体,让您可以在“mozconfig”文件中定义选项:
http://mxr.mozilla.org/mozilla-central/source/ client.mk#138

You could write another shell script that executes all those commands, then prints out variable assignments that make can use. Run the script, pipe its output to a file, then include that file from your Makefile. For example:

Makefile:

all:
    echo $(FOO)

test.mk: test.sh
    ./
lt; > $@

include test.mk

test.sh

echo "FOO=1"

Running "make" in the directory containing this Makefile produces:

make: Entering directory `/home/luser/build/mktest'
Makefile:7: test.mk: No such file or directory
./test.sh > test.mk
make: Leaving directory `/home/luser/build/mktest'
make: Entering directory `/home/luser/build/mktest'
echo 1
1
make: Leaving directory `/home/luser/build/mktest'

make creates test.mk by running the shell script, then includes it. test.mk contains the output of test.sh, and is parsed as a Makefile. See http://www.gnu.org/software/make/manual/make.html#Include for more details.

We use a variant of this in Mozilla's client.mk to let you define options in a "mozconfig" file:
http://mxr.mozilla.org/mozilla-central/source/client.mk#138

痴骨ら 2024-08-14 02:19:55

重述:如何将 shell 变量放入 make 文件中?

类似于:

MYVAR := $(shell echo $(MYVAR)) <any_makefile_additions_here> 

因此,当还设置了名为 MYVAR 的环境变量时,这在 MAKEFILE 中定义了 MYVAR。

Restatement: How do I get a shell variable into a make file?

Something like:

MYVAR := $(shell echo $(MYVAR)) <any_makefile_additions_here> 

So, this defines MYVAR inside a MAKEFILE when an environment variable named MYVAR is also set.

尛丟丟 2024-08-14 02:19:55

可能有趣的是,为了覆盖 makefile 中已定义的选项, make 支持(我指的是 GNU Make 3.82,但也可能是其他版本)选项 -e
示例:

Makefile:

CC=gcc
...

运行 make:

CC=gcc-4.7
make -e

将使用 gcc-4.7 而不是 gcc。

It might be of interest, that, in order to override an option that is already defined in a makefile, make supports (I am referring to GNU Make 3.82, but other version probably too) the option -e.
Example:

Makefile:

CC=gcc
...

Run make:

CC=gcc-4.7
make -e

will use gcc-4.7 instead of gcc.

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