当前位置：文江博客话题详情

VHDL：如何在输入输出端口上设置值？

发布于 2024-08-06 16:56:49 字数 160 浏览 3 评论 0原文

我正在尝试测试 VHDL 组件，但我似乎无法获取这个输入端口给我任何行为。我尝试将端口设置为从“1”到“-”的所有值，但在模拟中它仍然显示为“U”。有什么建议可能有什么问题吗？

原文

分享到QQ

分享到微博

如果你对这篇内容有疑问，欢迎到本站社区发帖提问参与讨论，获取更多帮助，或者扫码二维码加入 Web 技术交流群。

发布评论

需要登录才能够评论，你可以免费注册一个本站的账号。

失眠症患者 2024-08-13 16:56:50

当使用 inout 端口时，当 VHDL 语句显然太复杂而无法综合推断 IOBUF 时，我被实例化 OBUF 而不是 IOBUF 的综合工具所困扰。以下是令我困扰的情况的简化示例（假设所有信号均为 std_logic）：

data_a <= '1' when assert_a = '1' else '0';
data_b <= 'Z' when float_b = '1' else '0';  
data_inout <= data_a when choose_a = '1' else data_b;

在我的失败案例中，综合为 data_inout 生成了一个 OBUF。我本来期望 IOBUF 能够处理 choice_a='0' 和 float_b='1' 的情况，因为应该将 'Z' 分配给 data_inout，但这不是我得到的。

When using an inout port, I've been bitten by a synthesis tool instantiating an OBUF instead of an IOBUF when the VHDL statements were apparently too complicated for synthesis to infer the IOBUF. The following is a simplified example (assume all signals are std_logic) of the situation that bit me:

data_a <= '1' when assert_a = '1' else '0';
data_b <= 'Z' when float_b = '1' else '0';  
data_inout <= data_a when choose_a = '1' else data_b;

In my failure case, synthesis generated an OBUF for data_inout. I would have expected an IOBUF to handle the case of choose_a='0' and float_b='1' because that should have assigned 'Z' to data_inout, but that's not what I got.

回复收藏 0 原文

醉酒的小男人 2024-08-13 16:56:49

对于 Inout 端口（例如在 RAM 中）：

....
port(
    data    :inout std_logic_vector (DATA_WIDTH-1 downto 0);
....
-- Memory Write Block
-- Write Operation : When we = 1, cs = 1
  MEM_WRITE: process (address, cs, we, data, address_1, cs_1, we_1, data_1) begin
    if (cs = '1' and we = '1') then
       mem(conv_integer(address)) <= data;
    end if;
  end process;

 -- Tri-State Buffer control
  data <= data_out when (cs = '1' and oe = '1' and we = '0') else (others=>'Z');

 -- Memory Read Block
  MEM_READ: process (address, cs, we, oe, mem) begin
    if (cs = '1' and we = '0' and oe = '1') then
      data_out <= mem(conv_integer(address));
    else
      data_out <= (others=>'0');
    end if;
  end process;

您可以使用条件为 inout 分配数据读取和写入。读取数据时，由另一个模块驱动。当它写入时，由内部驱动。

例如，当由另一个模块驱动时（如在信号中），数据在所有“Z”和向量“0101010”之间解析。数据将驱动为“0101010”。
在其他情况下：其他模块必须通过全“Z”驱动数据，然后内部信号才能将其值写入数据。

For Inout port (for example in RAM):

....
port(
    data    :inout std_logic_vector (DATA_WIDTH-1 downto 0);
....
-- Memory Write Block
-- Write Operation : When we = 1, cs = 1
  MEM_WRITE: process (address, cs, we, data, address_1, cs_1, we_1, data_1) begin
    if (cs = '1' and we = '1') then
       mem(conv_integer(address)) <= data;
    end if;
  end process;

 -- Tri-State Buffer control
  data <= data_out when (cs = '1' and oe = '1' and we = '0') else (others=>'Z');

 -- Memory Read Block
  MEM_READ: process (address, cs, we, oe, mem) begin
    if (cs = '1' and we = '0' and oe = '1') then
      data_out <= mem(conv_integer(address));
    else
      data_out <= (others=>'0');
    end if;
  end process;

You assign data read and write for inout with a condition. When data is read, it is driven by another module. When it writes, it is driven by internal.

When driven by another module (as in signal), data is resolved between all 'Z' and a vector "0101010" for example. The data will driven as "0101010".
In the other case: the other module must drive data by all "Z" and then the internal signal can put its value to data.

回复收藏 0 原文