在verilog编译中查找所有依赖项
我正在尝试以廉价且准确的方式预测构建流程的所有 SystemVerilog 依赖项。过度预测依赖项并找到一些不是 sv 依赖项的 Verilog 文件是可以的，但我不想错过任何依赖项。
我实际上是否必须解析 Verilog 才能确定其所有依赖项？有tick-include预处理器宏，但那些tick-include似乎并没有加载当前正在编译的所有代码。有一个 SYSTEM\_VERILOG\_PATH 环境变量。我是否需要解析该 SYSTEM\_VERILOG\_PATH 变量中的每个 SystemVerilog 文件以确定在哪些文件中定义了哪些模块？
I'm trying to cheaply and accurately predict all the SystemVerilog dependencies for a build flow. It is ok to over-predict the dependencies and find a few Verilog files that aren't sv dependencies, but I don't want to miss any dependencies.
Do I actually have to parse the Verilog in order to determine all its dependencies? There are tick-include preprocessor macros, but those tick-include don't seem to load all the code currently getting compiled. There is a SYSTEM\_VERILOG\_PATH environment variable. Do I need to parse every SystemVerilog file in that SYSTEM\_VERILOG\_PATH variable in order to determine which modules are defined in which files?
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一种好方法（如果这是可综合代码）是使用综合工具文件列表（例如 Altera 的 .qsf）。这往往是完整的，但如果不完整，您可以查看构建日志以查找它发现的丢失文件。
One good way (if this is synthesizable code) is to use your synthesis tool file list (e.g. .qsf for Altera). That tends to be complete, but if it isn't, you can look at the build log for missing files that it found.
从易于编译的环境中，可以转储源文件
（例如节奏
）
但如果你是从头开始，恐怕没有简单的解决方案。我会选择实用的一种：拥有一个配置文件，其中包含包含 .sv 文件的所有目录，然后编译其中的所有内容。如果您的项目具有正确的文件结构，您还可以通过为每个主要块提供配置文件来模块化它。
希望有帮助。
From a readily compiled environment it is possible to dump the source files
(e.g. Cadence
)
but if you are starting from scratch I am afraid there is no easy solution. I would go for the pragmatic one: have a config file with all the directories that contain .sv files and then compile everything in it. If your project has a proper file structure, you could also modularize this by supplying config files for every major block.
Hope that helps.
我知道 Questa 有一个命令行选项，在您编译设计后，它会为您生成一个 makefile，其中包含所有依赖项。不知道其他模拟器有没有这个功能。
另一种选择是在模拟器中浏览并转储已编译的库。您可能不会获得编译模块的实际文件名，但解析所有 verilog 文件以获取编译库中显示的模块名称会容易得多。
I know Questa has a command line option where it will generate a makefile for you with all the dependencies in it after you have compiled your design. I'm not sure if the other simulators have that.
Another option is to browse and dump your compiled library in your simulator. You probably won't get the actual filenames the modules are compiled from, but it'll be a lot easier to parse all your verilog files for the module names that show up in the compiled library.