Altera的Quartus可以编译VHDL并为您提供代表VHDL信号的顶级原理图块。 Xilinx ISE 也是如此。 它不是开源软件，但可以免费下载和使用。
Altera's Quartus can compile VHDL and provide you with the top-level schematic blocks, representing the VHDL signals. Ditto with Xilinx ISE. Its not open source software, but it is free to download and use.
Synplify Pro 和 Synplify Premier 有一个 RTL 查看器，是我见过的程序中我最喜欢的程序。 我还在Xilinx ISE、Altera 的Quartus 和Mentor 的HDL 设计器中看到了RTL 查看器。
Synplify Pro and Synplify Premier has an RTL viewer and is my preferred program of the ones I have seen. I have also seen RTL viewers in Xilinx ISE, Altera's Quartus and Mentor's HDL designer.
Mentor's HDL designer is for this purpose, but it's not free, although you can probably get a discounted student version.
As thetrus noted Quartus has an RTL viewer as well, but the quality of diagrams produced by it is pretty poor - you can't really use them for documentation. They're most useful for catching synthesis bugs.
HDL Works in Ede Netherlands has EASE which is similar to Mentor's HDL Designer but much more nimble and far less expensive, I have used both. Of the two, EASE is far easier to get going with and maintain from my experience. I found the Mentor tool hard to use and unstable but I assume it has since been improved. EASE is much more intuitive and the focus is still on the code and less on tool use. Unlike the post-synthesis tools from Xilinx, Synopsys and others, the HDL Works tool and the Mentor HDL Designer are pre-synthesis. A tool that is somewhat in-between pre and post is Sigasi. I have seen but as yet have not used the latter. It looks promising. Links: https://www.hdlworks.com/products/ease/index.html
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Altera的Quartus可以编译VHDL并为您提供代表VHDL信号的顶级原理图块。 Xilinx ISE 也是如此。 它不是开源软件，但可以免费下载和使用。
Altera's Quartus can compile VHDL and provide you with the top-level schematic blocks, representing the VHDL signals. Ditto with Xilinx ISE. Its not open source software, but it is free to download and use.
无论如何，没有什么是开源的。 不久前，我为 verilog 设计寻找类似的东西，但没有成功。
There's nothing open-sourced anyways. A while back, I looked for something simliar for verilog designs with no success.
Synplify Pro 和 Synplify Premier 有一个 RTL 查看器，是我见过的程序中我最喜欢的程序。 我还在Xilinx ISE、Altera 的Quartus 和Mentor 的HDL 设计器中看到了RTL 查看器。
Synplify Pro and Synplify Premier has an RTL viewer and is my preferred program of the ones I have seen. I have also seen RTL viewers in Xilinx ISE, Altera's Quartus and Mentor's HDL designer.
Mentor 的 HDL 设计器就是用于此目的，但它不是免费的，尽管您可能可以获得打折的学生版。
正如 thetrus 所指出的，Quartus 也有一个 RTL 查看器，但它生成的图表的质量相当差 - 你不能真正将它们用于文档。 它们对于捕获综合错误最有用。
Mentor's HDL designer is for this purpose, but it's not free, although you can probably get a discounted student version.
As thetrus noted Quartus has an RTL viewer as well, but the quality of diagrams produced by it is pretty poor - you can't really use them for documentation. They're most useful for catching synthesis bugs.
荷兰Ede的HDL Works有EASE，类似于Mentor的HDL Designer
但更灵活且便宜得多，我都使用过。 根据我的经验，两者中，EASE 更容易使用和维护。 我发现 Mentor 工具很难使用并且不稳定，但我认为它已经得到了改进。 EASE 更加直观，重点仍然是代码而不是工具的使用。 与 Xilinx、Synopsys 等公司的后综合工具不同，HDL Works 工具和 Mentor HDL Designer 是预综合的。 Sigasi 是一个介于前置和后置之间的工具。 我见过但尚未使用后者。 看起来很有希望。
链接：
https://www.hdlworks.com/products/ease/index.html
http://www.sigasi.com/
HDL Works in Ede Netherlands has EASE which is similar to Mentor's HDL Designer
but much more nimble and far less expensive, I have used both. Of the two, EASE is far easier to get going with and maintain from my experience. I found the Mentor tool hard to use and unstable but I assume it has since been improved. EASE is much more intuitive and the focus is still on the code and less on tool use. Unlike the post-synthesis tools from Xilinx, Synopsys and others, the HDL Works tool and the Mentor HDL Designer are pre-synthesis. A tool that is somewhat in-between pre and post is Sigasi. I have seen but as yet have not used the latter. It looks promising.
Links:
https://www.hdlworks.com/products/ease/index.html
http://www.sigasi.com/