有谁知道如何启用 ARM FIQ?
有谁知道如何启用 ARM FIQ?
Does anyone know how to enable ARM FIQ?
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有谁知道如何启用 ARM FIQ?
Does anyone know how to enable ARM FIQ?
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除了在管理模式下启用或禁用 IRQ/FIQ 之外,您无需在 ARM 上进行任何特殊设置即可使用它,除非系统(运行 ARM 芯片的系统)已在硬件中禁用它(根据您的评论,情况并非如此,因为您看到 FIQ 输入引脚驱动正确)。
要在管理模式下启用 FIQ:
对于普通 IRQ 可以执行类似的操作,但使用 #0x80 而不是 #0x40。
Other than enabling or disabling the IRQ/FIQ while you're in supervisor mode, there's no special setup you should have to do on the ARM to use it, unless the system (that the ARM chip is running in) has disabled it in hardware (based on your comment, this is not the case since you're seeing the FIQ input pin driven correctly).
To enable FIQ in supervisor mode:
A similar thing can be done for normal IRQs, but using #0x80 instead of #0x40.
芯片制造商可以使用 trustzone 扩展向您关闭 FIQ。
Trustzone 创建一个安全的世界和一个正常的世界。 安全世界有自己的监管者、用户和内存空间。 这个想法是为了路由安全操作,这样它们就不会离开芯片,并且即使扫描总线上的引脚也无法被追踪。 我认为在 OMAP 中它用于一些加密操作。
重置时,核心以安全模式启动。 它设置安全监视器(安全和非安全世界之间的网关),此时可以将 FIQ 设置为路由到监视器。 我认为可能是设置了 SCR.FIQ 位,然后所有 FIQ 都会忽略 CPSR.F 的值并进入监视模式。 查看 ARM ARM,但如果我没记错的话,如果发生这种情况,您将无法从不安全的操作系统代码中得知。 然后监视器将重置正常世界寄存器并执行异常返回,并将 PC 设置为重置异常向量。
内核将进入监视模式中断,执行其操作并返回。
抱歉,我无法在评论中回答你,我没有足够的声誉,你总是可以解决这个问题;),但我希望你看到这个
The FIQ can be closed off to you by the chip manufacturer using trustzone extensions.
Trustzone creates a Secure world and a normal world. The secure world has its own supervisor, user and memory space. The idea is for secure operations to be routed so they never leave the chip and cannot be traced even if you scan the pins on the bus. I think in OMAP it is used for some cryptography operations.
On Reset the core starts in secure mode. It sets up the secure monitor (gateway between secure and non-secure world) and at this time FIQ can be setup to be routed to the monitor. I think it is the SCR.FIQ bit that may be set and then all FIQs ignore the value of CPSR.F and go to monitor mode. Check out the ARM ARM but if I remember correctly if this is happening there is no way for you to know from nonsecure OS code. Then the monitor will reset the Normal world registers and doing an exception return with PC set to the reset exception vector.
The core will take an interrupt to monitor mode, do its thing and return.
Sorry I can't answer you in the comments, I don't have enough reputation, you could always fix that ;), but I hope you see this