b <= "1000" when a = "00" else
"1000" when a = "01" else
"1000" when a = "10" else
"1000" when a = "11";
与案例陈述的组合过程
最常用的构造是过程。 在此过程中，您可以编写 case 语句或级联 if 语句。 这里还有更多的冗余。 您拥有流程的框架代码（开始、结束）和敏感度列表。 这并不是一个很大的努力，但是当我起草这个时，我将 b 放在敏感度列表中，而不是 a 中。 很容易犯小错误。 您还需要指定在其他情况下会发生什么。
process(a)
begin
case a is
when "00" => b <= "1000";
when "01" => b <= "0100";
when "10" => b <= "0010";
when "11" => b <= "0001";
when others => assert "unreachable" severity failure;
end case;
end process;
选定和条件信号分配的问题在于其语法中没有系统。 含义几乎相同，但语法的不同足以让您感到困惑。 我认识许多工程师，他们的办公桌上永远放着一份《Doulos Golden Reference Guide to VHDL》。 这对斗洛斯来说是件好事，因为他们的名字总是被提及。
Sometimes, there are more than one way to do something. OK, most of the time, you can do things in many ways in VHDL. Look at situation where you want to assign different values to a signal, based on the value of another signal.
Selected Signal Assignment
The most specific way to do this is with as selected signal assignment. Based on several possible values of b, you assign a value to a. No redundancy in the code here.
with a select b <=
"1000" when "00",
"0100" when "01",
"0010" when "10",
"0001" when "11";
Conditional Signal Assignment
The construct of a conditional signal assignment is a little more general. For each option, you have to give a condition. This means that you could write any boolean expression as a condition, which give you more freedom than equality checking. While this construct would give you more freedom, there is a bit more redundancy too. We had to write the equality check (a =) on every line. If you use a signal with a long name, this will make your code bulkier. Also, the separator that's used in the selected signal assingment was a comma. In the conditional signal assingment, you need the else keyword. More code for the same functionality.
b <= "1000" when a = "00" else
"1000" when a = "01" else
"1000" when a = "10" else
"1000" when a = "11";
Combinational Process with Case Statement
The most generally usable construct is a process. Inside this process, you can write a case statement, or a cascade of if statements. There is even more redundancy here. You the skeleton code for a process (begin, end) and the sensitivity list. That's not a big effort, but while I was drafting this, I had put b in the sensitivity list instead of a. Easy to make a small misstake. You also need to specify what happens in the other cases.
process(a)
begin
case a is
when "00" => b <= "1000";
when "01" => b <= "0100";
when "10" => b <= "0010";
when "11" => b <= "0001";
when others => assert "unreachable" severity failure;
end case;
end process;
While this last code snippet is the largest and perhaps most error-prone, it is probably also the most common. It uses two familiar and often-used constructs: the process and the case statements.
The problem with the selected and conditional signal assignments is that there is no system in their syntax. The meaning is almost identical, but the syntax is just different enough to throw you off. I know many engineers who permanently have a copy of the Doulos Golden Reference Guide to VHDL lying on their desks. Which is good for Doulos, because their name gets mentioned all the time.
与 C++ 中的 OOP 相同：您可以定义一个接口和多个实现。 在 VHDL 中为同一器件创建仿真和综合模型非常有用。
语言模型固有的低开销并行性。 这有点让我想起数据流语言。
实际上，C++ 中有 SystemC 库，它实现了并行执行语义。 您可以轻松下载并尝试：http://www.systemc.org。 我正在研究 C++ 到 RTL 的综合。 所以我希望在 4-5 年内所有硬件开发都将使用 SystemC 和 C++ 来完成。
The best feature of VHDL — that it is used to design and implement hardware. :)
The ability to have several different implementations (architectures) of a single interface, and exchange them easily.
The same with OOP in C++: you can define one interface and many implementations. It is very useful in VHDL to create simulation and synthesis models for the same device.
The low-overhead parallelism inherent to the language model. It sort of reminds me of dataflow languages.
Actually, there is SystemC library to C++ which implements parallel execution semantics. You can easily download and try this: http://www.systemc.org. I'm working on C++-to-RTL synthesis. So I hope in 4-5 years all hardware development will be done using SystemC and C++.
What are some really useful but esoteric language features in VHDL
Firstly, I don't buy into the theory that VHDL has 'esoteric' features. However, the prevalent 'styles' of VHDL that exist in the wild are most often influenced by what subset of VHDL is supported by hardware synthesizers.
The equation in the VHDL world is very simple: if tools support a language subset, it will be used. If not, the feature will likely be underused.
especially when you compare VHDL to other (normal) programming languages.
Note that VHDL is not a programming language. Rather, it is a language for describing discrete event systems (with an 'accidental' consequence that it can be used to describe digital hardware). I suppose that the comparison to programming languages stems from VHDL looking like some actual programming languages.
Now on to some actual answers to the OP's question.
What are some really useful but esoteric language features in VHDL...
Here's my pick, in no particular order.
Architectures: By far, the ability to select different architectures for an interface is the most useful feature VHDL has and which is being used at all times.
Generators: using generators you can pretty easily describe complex regular hardware structures. Think multipliers, adders, complex pipelines and the like. Unfortunately, many tools make a mess out of the generated output.
Blocks: A cheap way to sub-divide your design into sub-blocks; not all tools support it though.
Signal resolution: Rather useful when simulating circuits and the like, not so for hardware synthesis.
Attributes: A great way to attach instructions to the simulator/synthesizer to help it out in finding the best way to implement your circuit. While this can in most cases be done with command line options to the synthesizer/mapper/p&r tools, attributes feel much more natural, as all the info needed to produce your piece of hardware is confined to a single place.
VHDL 的许多“深奥”功能都起源于 Ada。 我提到这一点是因为我不是 Ada 专家，但学习 Ada 极大地提高了我对 VHDL 所能实现的能力的认识。
Quite a few of VHDL's "esoteric" features have their origin in Ada. I mention this because I'm not an Ada expert, but learning Ada has greatly improved my vision of what can be accomplished in VHDL.
Conditional signal assignment is the same as a case statement - i.e. equal weight branches. Selected signal assignment is a priority encoder structure - i.e. equivalent to nested if/then/else statements. Note that all concurrent assignment statements in vhdl are identically equivalent to a process with a sensitivity list composed of the signals on the right hand side of the assignment operator.
My favourite esoteric features are configurations (which are especially useful when you have multiple architectures of the same entity) and access types. These allow one to create dynamic data structures. Not useful for hardware design, but very useful for testbench creation. Method overloading my argument type signature also makes for very readable code - and is a feature sadly lacking in SystemVerilog.
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用户定义的物理类型，例如“角度”、“电压”、“温度系数”，然后您可以在其中编写诸如
temp <= 45 deg;< /code> 或伏特 <= 3.3 V；。User-defined physical types like "angle", "voltage", "temperature_coefficient", where you can then write stuff like
temp <= 45 deg;orvolt <= 3.3 V;.有时，做某事有不止一种方法。 好的，大多数时候，您可以用 VHDL 以多种方式完成任务。 查看您想要根据另一个信号的值向一个信号分配不同值的情况。
选定信号分配
最具体的方法是使用选定信号分配。 根据
b的几个可能值，您可以为a分配一个值。 这里的代码没有冗余。条件信号分配
条件信号分配的构造更为通用。 对于每个选项，您都必须给出一个条件。 这意味着您可以编写任何布尔表达式作为条件，这给您比相等检查更多的自由。 虽然这种结构会给你更多的自由，但也有更多的冗余。 我们必须在每一行上编写相等性检查（
a =）。 如果您使用名称很长的信号，这将使您的代码变得更庞大。 此外，所选信号分配中使用的分隔符是逗号。 在条件信号分配中，您需要else关键字。 相同功能的更多代码。与案例陈述的组合过程
最常用的构造是过程。 在此过程中，您可以编写 case 语句或级联 if 语句。 这里还有更多的冗余。 您拥有流程的框架代码（开始、结束）和敏感度列表。 这并不是一个很大的努力，但是当我起草这个时，我将
b放在敏感度列表中，而不是a中。 很容易犯小错误。 您还需要指定在其他情况下会发生什么。虽然最后一个代码片段是最大的，而且可能是最容易出错的，但它也可能是最常见的。 它使用两个熟悉且常用的结构：过程和案例语句。
选定和条件信号分配的问题在于其语法中没有系统。 含义几乎相同，但语法的不同足以让您感到困惑。 我认识许多工程师，他们的办公桌上永远放着一份《Doulos Golden Reference Guide to VHDL》。 这对斗洛斯来说是件好事，因为他们的名字总是被提及。
Sometimes, there are more than one way to do something. OK, most of the time, you can do things in many ways in VHDL. Look at situation where you want to assign different values to a signal, based on the value of another signal.
Selected Signal Assignment
The most specific way to do this is with as selected signal assignment. Based on several possible values of
b, you assign a value toa. No redundancy in the code here.Conditional Signal Assignment
The construct of a conditional signal assignment is a little more general. For each option, you have to give a condition. This means that you could write any boolean expression as a condition, which give you more freedom than equality checking. While this construct would give you more freedom, there is a bit more redundancy too. We had to write the equality check (
a =) on every line. If you use a signal with a long name, this will make your code bulkier. Also, the separator that's used in the selected signal assingment was a comma. In the conditional signal assingment, you need theelsekeyword. More code for the same functionality.Combinational Process with Case Statement
The most generally usable construct is a process. Inside this process, you can write a case statement, or a cascade of if statements. There is even more redundancy here. You the skeleton code for a process (begin, end) and the sensitivity list. That's not a big effort, but while I was drafting this, I had put
bin the sensitivity list instead ofa. Easy to make a small misstake. You also need to specify what happens in theothercases.While this last code snippet is the largest and perhaps most error-prone, it is probably also the most common. It uses two familiar and often-used constructs: the process and the case statements.
The problem with the selected and conditional signal assignments is that there is no system in their syntax. The meaning is almost identical, but the syntax is just different enough to throw you off. I know many engineers who permanently have a copy of the Doulos Golden Reference Guide to VHDL lying on their desks. Which is good for Doulos, because their name gets mentioned all the time.
VHDL 的最佳功能是用于设计和实现硬件。 :)
与 C++ 中的 OOP 相同：您可以定义一个接口和多个实现。 在 VHDL 中为同一器件创建仿真和综合模型非常有用。
实际上，C++ 中有 SystemC 库，它实现了并行执行语义。 您可以轻松下载并尝试：http://www.systemc.org。 我正在研究 C++ 到 RTL 的综合。 所以我希望在 4-5 年内所有硬件开发都将使用 SystemC 和 C++ 来完成。
The best feature of VHDL — that it is used to design and implement hardware. :)
The same with OOP in C++: you can define one interface and many implementations. It is very useful in VHDL to create simulation and synthesis models for the same device.
Actually, there is SystemC library to C++ which implements parallel execution semantics. You can easily download and try this: http://www.systemc.org. I'm working on C++-to-RTL synthesis. So I hope in 4-5 years all hardware development will be done using SystemC and C++.
首先，我不相信 VHDL 具有“深奥”特性的理论。 然而，普遍存在的 VHDL“风格”通常受到硬件合成器支持的 VHDL 子集的影响。
VHDL 世界中的等式非常简单：如果工具支持某个语言子集，就会使用它。 如果没有，该功能可能不会得到充分利用。
请注意，VHDL 不是一种编程语言。 相反，它是一种用于描述离散事件系统的语言（其“意外”结果是它可以用于描述数字硬件）。 我认为与编程语言的比较源于 VHDL 看起来像一些实际的编程语言。
现在来回答OP问题的一些实际答案。
这是我的选择，排名不分先后。
Firstly, I don't buy into the theory that VHDL has 'esoteric' features. However, the prevalent 'styles' of VHDL that exist in the wild are most often influenced by what subset of VHDL is supported by hardware synthesizers.
The equation in the VHDL world is very simple: if tools support a language subset, it will be used. If not, the feature will likely be underused.
Note that VHDL is not a programming language. Rather, it is a language for describing discrete event systems (with an 'accidental' consequence that it can be used to describe digital hardware). I suppose that the comparison to programming languages stems from VHDL looking like some actual programming languages.
Now on to some actual answers to the OP's question.
Here's my pick, in no particular order.
VHDL 的许多“深奥”功能都起源于 Ada。 我提到这一点是因为我不是 Ada 专家，但学习 Ada 极大地提高了我对 VHDL 所能实现的能力的认识。
Quite a few of VHDL's "esoteric" features have their origin in Ada. I mention this because I'm not an Ada expert, but learning Ada has greatly improved my vision of what can be accomplished in VHDL.
条件信号分配与 case 语句相同 - 即等权分支。 选定的信号分配是优先级编码器结构 - 即相当于嵌套的 if/then/else 语句。 请注意，vhdl 中的所有并发赋值语句都等同于具有由赋值运算符右侧的信号组成的敏感列表的进程。
我最喜欢的深奥功能是配置（当您拥有同一实体的多个架构时特别有用）和访问类型。 这些允许人们创建动态数据结构。 对于硬件设计没有用，但对于测试平台创建非常有用。 方法重载我的参数类型签名也使得代码非常可读 - 并且是 SystemVerilog 中遗憾地缺乏的功能。
保罗.
Conditional signal assignment is the same as a case statement - i.e. equal weight branches. Selected signal assignment is a priority encoder structure - i.e. equivalent to nested if/then/else statements. Note that all concurrent assignment statements in vhdl are identically equivalent to a process with a sensitivity list composed of the signals on the right hand side of the assignment operator.
My favourite esoteric features are configurations (which are especially useful when you have multiple architectures of the same entity) and access types. These allow one to create dynamic data structures. Not useful for hardware design, but very useful for testbench creation. Method overloading my argument type signature also makes for very readable code - and is a feature sadly lacking in SystemVerilog.
Paul.
我所知道的最深奥的就是三个原则的结合：
现在这个表达式是什么？：foo'\'bar\
它是 foo 的 \'bar\ 属性。
我想没有任何 vhdl 词法分析器能幸存下来。
The most esoteric thing I know is the combination of three principles:
Now what is this expression?: foo'\'bar\
It is the \'bar\ attribute of foo.
I guess no vhdl lexer survives this.
您可以在包中包含信号。
您可以在配置中创建新端口。
您可以根据返回类型重载函数。
您可以在实体中定义可从架构中使用的信号。 据我所知，这对任何东西都没有用，但它就在那里。
You can have signals in a package.
You can create new ports in a configuration.
You can overload functions based on return type.
You can define signals in an entity, that can be used from the architecture. This is not useful for anything that I know of, but it's there.