如何在 Automake 中不链接的情况下进行编译?
我是 Automake 的新手,我正在尝试在不链接的情况下进行编译。 我的目标是使用 Automake 生成一个简单的 Makefile,如下所示。
CFLAG = -Wall
build: Thread.o
Thread.o: Thread.cc Thread.h
g++ $(CFLAG) -c Thread.cc
clean:
rm -f *.o
到目前为止,我的尝试已将我带到以下 Makefile.ac。
noinst_PROGRAMS = thread
thread_SOURCES = Thread.cc
EXTRA_DIST= Thread.h
如何模拟我的原始 Makefile?
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一种方法是通过提供不链接的链接命令来欺骗 Automake:
除此之外,如果 Automake 没有这样的功能,我也不会感到惊讶。
One way is to do this is to fool Automake by providing link command that does not link:
Other than that, I wouldn't be suprised if Automake did not have such feature.
对于您的示例,您可以直接要求 Automake 构建您的
.o
文件,eg:我相信这是一个隐式规则,因此您不会在输出生成文件。
一般来说,Automake 生成的变量包含每个可执行文件或库目标所需的所有对象。 在
Makefile
中使用它们非常简单,因为它只是通过将 _OBJECTS 附加到目标名称来生成它们的名称。 您可以在Makefile.am
中创建自己的目标,如下所示:然后您可以像这样构建 Thread.o(以及
thread
所需的任何其他对象):或者如果您有多个目标
foo
、bar
和baz
,您可以在Makefile.am
中创建仅编译目标像这样:这里唯一的痛苦是您需要根据
Makefile.am
中的目标自行维护此列表。 您可以在命令行中调用它,如下所示:For your example, you can just ask Automake to build your
.o
file directly, e.g.:I believe this is an implicit rule, so you won't see it in the output Makefile.
In general, Automake generates variables containing all the objects required for each executable or library target. It's pretty straightforward to use them in your
Makefile
, since it just generates their names by appending _OBJECTS to the target name. You could make your own target inMakefile.am
like this:Then you could build just Thread.o (and any other objects needed for
thread
) like this:Or if you had multiple targets
foo
,bar
, andbaz
, you could make your compile-only target inMakefile.am
like this:The only pain here is that you'll need to maintain this list yourself based on the targets in your
Makefile.am
. You can invoke it at the command line like this:Automake 并不是为了生成对象而设计的。 它将构建程序或库。
如果不知道为什么要编译单个目标文件而不是其他文件,则很难回答您的问题。 也许对您的“真正”问题有一个更清晰的答案。
您可以编写的
Makefile.am
是生成的
Makefile
将构建一个仅包含libThread.o
的库libThread.a
>,因为*.a
库只是目标文件的集合,因此不涉及链接。上面的
Makefile.am
还会导致发出的Makefile
包含编译libThread.o
的规则,因此您可以添加构建:
规则,如果你愿意的话。如果您确实希望 Automake 发出此编译规则,但不构建库,则可以使用
Now you are明确要求仅在键入
Thread.$(OBJEXT)
>make build,如原始Makefile
中一样。(Automake 使用
.$(OBJEXT)
而不是.o
来支持 DOS 变体中的.obj
等扩展。)Automake is not designed to produce object. It will build either programs or libraries.
It's hard to answer your question without knowing why you'd want to compile a single object file and not something else. Maybe there is a cleaner answer to your "real" problem.
A
Makefile.am
you could write isThe resulting
Makefile
would build a librarylibThread.a
containing onlylibThread.o
, ans because*.a
libraries are just a collection of object files there is no linking involved.The above
Makefile.am
also causes the emittedMakefile
to contain rules to compilelibThread.o
, so you can add abuild:
rule if you like.If you really want Automake to emit this compile rule, but not build the library, you could go with
Now you are explicitely requiring the file
Thread.$(OBJEXT)
to be built only when you typemake build
, as in your originalMakefile
.(Automake uses
.$(OBJEXT)
rather than.o
to support extensions like.obj
in DOS variants.)首先,automake是一个自动make制作Makefile的工具; make 本身是一个完全不同的野兽(我很确定您正在寻找的是一个 make 解决方案)。
这是最简单的基于 GNU 的 Makefile 来完成您想要的任务:
这会填充如下内容(默认情况下)(请将 4 个空格空格更改为硬制表符):
COMPILE.cpp 和 OUTPUT_OPTION 宏当然默认扩展为 GNU make指定值且不可移植; $< 是 AT&T Make 标准语法,尽管根据 pmake(1) 的联机帮助页。
GNU make 有一个可以使用的隐式与显式规则、模式、后缀等的概念,但这并不是可移植到所有版本的 make,因此这就是为什么所有 Makefile 都以目标和变量的形式清楚地拼写为POSIX 没有描述如何编写 Makefile 的许多所需场景。
运行 gmake -p 了解更多详细信息,并查看 gmake 的 texinfo 手册中隐式、显式规则、模式、后缀等主题。
First off, automake is a tool to auto make making Makefiles; make in and of itself is a whole different beast (and I'm pretty sure that what you were looking for was a make solution).
Here's the easiest GNU based Makefile to accomplish what you want:
This fills in something (by default) like the following (please change 4-space whitespace to hard tabs):
The COMPILE.cpp and OUTPUT_OPTION macros of course expand by default to GNU make specified values and aren't portable; $< is AT&T Make standard syntax though according to pmake(1)'s manpage though.
GNU make has a concept of implicit vs explicit rules, patterns, suffixes, etc that you could use, but that's not portable to all versions of make, and hence that's why all of the Makefile is plainly spelled out in terms of targets and variables as POSIX doesn't describe many of the desired scenarios for how one should write a Makefile.
Run gmake -p for more details and take a look at the texinfo manual for gmake in the topic of implicit, explicit rules, patterns, suffixes, etc.