读取CPU缓存内容
有没有办法读取CPU缓存内容？ 架构适用于 ARM。
我正在使一系列地址无效，然后想确定它是否无效。 虽然我可以在有或没有无效和检查无效的情况下读取和写入地址范围，但我想知道是否可以读取缓存内容
谢谢！
Is there any way to read the CPU cache contents?
Architecture is for ARM.
I m invalidating a range of addresses and then want to make sure whether it is invalidated or not.
Although I can do read and write of the range of addresses with and without invalidating and checking the invalidation, I want to know whether it is possible to read the cache contents
Thanks!!
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ARM9 提供高速缓存操作和测试寄存器，允许您检查高速缓存的状态。 这是一个合理的起点：
http: //infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0151c/Chdcfejb.html
这些是特权指令，因此可能无法在您的目标平台上访问。
我将从一个简单的程序开始，该程序转储所有缓存行的状态。 这应该为您提供足够的信息，只需读取缓存标签提供的内存位置即可读取缓存中的数据。
ARM9 provides cache manipulation and test registers that allow you to examine the state of the cache. Here's a reasonable starting point:
http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0151c/Chdcfejb.html
These are privileged instructions so they may not be accessible on your target platform.
I'd start with a simple program that dumps the state of all the cache lines. That should give you enough information to read the data in the cache simply by reading the memory locations the cache tags provide.
我犹豫着要不要写这不可能，所以我写得非常困难。 可能没有通用的答案。 鉴于 CPU 缓存透明地工作，不可能在不更改缓存内容的情况下从连接的 CPU 读取其内容。 CPU缓存通常被实现为CAM（内容可寻址内存，关联内存），如果CPU尝试访问数据，则查找缓存，如果数据不存在，则从内存中获取，但恐怕这个过程对CPU是透明的。
选项是使用一种硬件观察模块并嗅探系统总线，将缓存连接到 RAM。 如果数据请求出现在总线上，则所请求的数据不在缓存中。
希望有更深入硬件知识的人能够提供帮助。
维基百科上有一个讨论 CPU 缓存的条目：
http://en.wikipedia.org/wiki/CPU_cache
I'm hesitant to write it's impossible, so I'm writing it's extremely hard. There is probably no generic answer. given that CPU cache works transparently it's not possible to read its content from attached CPU without altering cache content. CPU caches are usually implemented as CAM (content addressable memory, associative memory) if CPU tries to access data, the cache is looked up, if data are not there they are fetched from memory, but I'm afraid this process is transparent to CPU.
The option is to use a kind of HW observation module and sniff on system bus, which connects cache to RAM. If the request for data would appear on bus, then the requested data were not in cache.
hope someone with deeper HW knowledge will shed a light.
there is an entry on wikipedia discussing CPU caching:
http://en.wikipedia.org/wiki/CPU_cache
根据定义，读取缓存内容所需要做的就是加载缓存存储的内存位置。 如果缓存工作正常，它会从缓存中提取内容。
但是，如果您尝试读取指令缓存的内容，则这在体系结构上是相关的。 另外，您还需要考虑竞争条件。 用于读取缓存内容的指令可能会无意中覆盖缓存内容本身。
By definition, all you would need to do to read a cache content would be to load the memory location being stored by the cache. If the cache is working properly, it would extract the content from cache.
However, if you're trying to read the content of the I-cache, that is architecturally dependent. Plus, you will have race conditions to consider. The instruction for reading a cache content may inadvertently over-write the cache content itself.
如此线程中所述，仅使用 CPU 可能会导致缓存的内容要更改。 由于（大多数）缓存实现有意对 CPU 完全透明，因此您将无法直接从传统 CPU 上运行的软件中查看缓存的内容。
要做这样的事情需要一个缓存感知的CPU（带有用于控制缓存的特殊指令；我不知道这些是否真的存在），或者您需要安装一个单独的硬件模块来查看缓存。 我对此有两个想法：
用具有附加控制功能并且可以连接到系统总线来读取数据的控制器替换原来的缓存控制器。 该控制器位于 CPU 和缓存“之间”。
用
将辅助模块与原始缓存并行放置，并具有只读缓存访问权限。 使用特殊的中断线（或类似的硬件而非软件信号），CPU 可以触发将缓存转储到该模块的内存中，然后稍后（通过总线）将其读回。 该控制器不会影响您的缓存的操作； 它只允许您在任何给定时间拍摄快照。
As stated in this thread, simply using the CPU can cause the contents of cache to change. Since (most) cache implementations are intentionally completely transparent to the CPU, you will not be able to view the contents of the cache directly from within software running on traditional CPUs.
To do something like this would require either a cache-aware CPU (with special instructions for controlling the cache; I have no idea if these really exist), or you would need to install a separate HW module to view the cache. Here are 2 ideas I have for that:
Replace your original cache controller with one that has additional control features and can be connected to the system bus to read data. This controller sits "between" the CPU and cache.
Place a secondary module in parallel with the original cache, with read-only cache access. Using a special interrupt line (or similar hardware -NOT- software signal), the CPU could then trigger a dump of the cache into this module's memory, and then read it back (over a bus) later. This controller would not affect the operation of your cache; it would simply allow you to take snapshots at any given time.