有关 N 路组关联高速缓存步幅的信息
我在互联网上访问的一些资源对于如何设置关联缓存存在不同意见作品。
例如，硬件秘密似乎相信它的工作原理是这样的：
然后主 RAM 内存分为 可用的块数相同 内存缓存。 保留 512 KB 4 路集合关联示例， 主 RAM 将分为 2,048 块，块数相同 可以在内存缓存中使用。 每个内存块都链接到一个集合 缓存内的行数，就像 在直接映射缓存中。
http://www.hardwaresecrets.com/printpage/481/8
他们似乎是也就是说每个缓存块（4 个缓存行）映射到连续 RAM 的特定块。 他们说不连续的系统内存（RAM）块不能映射到同一个缓存块。
这是 hardwaresecrets 认为它是如何工作的图片 http://www.hardwaresecrets.com/fullimage.php?image=7864
与维基百科的设置关联缓存图片进行对比 http://upload.wikimedia.org/wikipedia /commons/9/93/Cache%2Cassociative-fill-both.png。
布朗不同意硬件秘密
考虑如果每个 缓存行有两组字段：两个 有效位、两个脏位、两个标签 字段和两个数据字段。 一套 的字段可以缓存一个数据 主存区，另一个为 恰好映射到的另一个区域 相同的缓存行。
http://www.spsu.edu/cs/faculty/bbrown/web_lectures/ cache/
也就是说，系统内存的非连续块可以映射到同一个缓存块。
系统内存上的非连续块和缓存块之间的关系是如何创建的。 我在某处读到这些关系是基于缓存跨度的，但除了它们存在之外，我找不到任何有关缓存跨度的信息。
谁是对的？ 如果实际使用了跨步，那么跨步是如何工作的？我有正确的技术名称吗？ 如何找到特定系统的步幅？ 是基于分页系统的吗？ 有人能给我一个详细解释 N 路组关联缓存的网址吗？
另请参阅： http://www.cs.umd.edu/class /sum2003/cmsc311/Notes/Memory/set.html
Several of the resources I've gone to on the internet have disagree on how set associative caching works.
For example hardware secrets seem to believe it works like this:
Then the main RAM memory is divided in
the same number of blocks available in
the memory cache. Keeping the 512 KB
4-way set associative example, the
main RAM would be divided into 2,048
blocks, the same number of blocks
available inside the memory cache.
Each memory block is linked to a set
of lines inside the cache, just like
in the direct mapped cache.
http://www.hardwaresecrets.com/printpage/481/8
They seem to be saying that each cache block(4 cache lines) maps to a particular block of contiguous RAM. They are saying non-contiguous blocks of system memory(RAM) can't map to the same cache block.
This is there picture of how hardwaresecrets thinks it works
http://www.hardwaresecrets.com/fullimage.php?image=7864
Contrast that with wikipedia's picture of set associative cache
http://upload.wikimedia.org/wikipedia/commons/9/93/Cache%2Cassociative-fill-both.png.
Brown disagrees with hardware secrets
Consider what might happen if each
cache line had two sets of fields: two
valid bits, two dirty bits, two tag
fields, and two data fields. One set
of fields could cache data for one
area of main memory, and the other for
another area which happens to map to
the same cache line.
http://www.spsu.edu/cs/faculty/bbrown/web_lectures/cache/
That is, non-contiguous blocks of system memory can map to the same cache block.
How are the relationships between non-contiguous blocks on system memory and cache blocks created. I read somewhere that these relationships are based on cache strides, but I can't find any information on cache strides other than that they exist.
Who is right?
If striding is actually used, how does striding work and do I have the correct technical name? How do I find the stride for a particular system? is it based on the paging system? Can someone point me to a url that explains N-way set associative cache in great detail?
also see:
http://www.cs.umd.edu/class/sum2003/cmsc311/Notes/Memory/set.html
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当我向学生教授缓存架构时，我从直接映射缓存开始。 一旦理解了这一点，您就可以将 N 路组关联缓存视为直接映射缓存的并行块。 要了解这两个数字可能都是正确的，您需要首先了解 set-assoc 缓存的用途。
它们旨在解决直接映射缓存中的“别名”问题，其中多个内存位置可以映射到特定的缓存条目。 维基百科的图中对此进行了说明。 因此，我们可以使用 N 路缓存来存储其他“别名”内存位置，而不是逐出缓存条目。
实际上，假设替换顺序是这样的，则硬件秘密图是正确的：主存储器的第一个块映射到 Way-1，然后第二个块映射到 Way-2，依此类推。 然而，同样可以将主存储器的第一块分布在多个路上。
希望这个解释有帮助！
PS：利用空间局部性，单个缓存行仅需要连续的内存位置。 至于你问题的后半部分，我相信你可能混淆了几个不同的概念。
When I teach cache memory architecture to my students, I start with a direct-mapped cache. Once that is understood, you can think of N-way set associative caches as parallel blocks of direct-mapped cache. To understand that both figures may be correct, you need to first understand the purpose of set-assoc caches.
They are designed to work around the problem of 'aliasing' in a direct-mapped cache, where multiple memory locations can map to a specific cache entry. This is illustrated in the Wikipedia figure. So, instead of evicting a cache entry, we can use a N-way cache to store the other 'aliased' memory locations.
In effect, the hardware secrets diagram would be correct assuming the order of replacement is such that the first chunk of main memory is mapped to Way-1 and then the second chunk to Way-2 and so on so forth. However, it is equally possible to have the first chunk of main memory spread over multiple Ways.
Hope this explanation helps!
PS: Contiguous memory locations are only needed for a single cache line, exploiting spatial locality. As for the latter part of your question, I believe that you may be confusing several different concepts.