用于测试平台的 verilog 或 systemc
我的任务是验证一些基于 verilog 的 RTL 代码。 现在，使用 verilog 编写 RTL 测试平台似乎非常困难（对我来说）。 所以我想尝试以下其中一项。 - 尝试向 RTL 提供 PLI 接口，从而调用“C 函数”进行测试 - 使用系统 'C 来连接 'C 函数
PS：我已经有一个广泛的 'C 代码，用于测试行为模型。 我是硬件编程领域的新手。 任何指示将不胜感激。
I am assigned with the task of verifying some verilog based RTL code. Now, coding the RTL testbench using verilog seems to be very difficult (for me). So I would like to try one of the following.
- Try providing a PLI interface to the RTL and thereby invoke 'C functions for testing
- Using system 'C for interfacing the 'C functions
PS: I already have a extensive 'C code that was used for testing the behavioral model. I am new to the world of hardware programming. Any pointers would be greatly appreciated.
如果你对这篇内容有疑问，欢迎到本站社区发帖提问 参与讨论，获取更多帮助，或者扫码二维码加入 Web 技术交流群。
绑定邮箱获取回复消息
由于您还没有绑定你的真实邮箱，如果其他用户或者作者回复了您的评论，将不能在第一时间通知您！
发布评论
评论（4）
如果您已经有大量用于测试行为模型的 C 代码，那么要做的就是添加一个 PLI（或 DPI）接口，该接口将允许您从 verilog 调用该 C 代码。
SystemC 基本上是 C++，具有许多允许您对硬件进行建模的类。 我不知道学习 SystemC 来完成您正在尝试的任务会对您有什么好处，因为您已经有了一个可以用来测试硬件的 C 模型。 学习 SystemC 对于你想要做的事情来说可能有点大材小用了。
供参考。 如果您想学习当今业界广泛使用的东西，那么我建议您学习 SystemVerilog。 现在的 SystemVerilog，基本上是 verilog，内置了一堆高级软件语言功能； 与“VMM”一起，一种“验证方法”（即一堆库）似乎在硬件验证领域风靡一时。
If you already have extensive C code that was used to test the behavioral model, then the thing to do is to just add a PLI (or DPI) interface that will allow you to call that c code from verilog.
SystemC is basically C++ with a lot of classes that allow you to model HW. I don't see how you would benefit from learning SystemC for the task you are attempting as you already have a C model available that you can test the HW against. Learning SystemC is probably overkill for what you are trying to do.
FYI. If you want to learn something that is heavily used in the industry today then I would suggest that you learn SystemVerilog. These days SystemVerilog, basically verilog with a bunch of high level software language features built in; along with "VMM", a "verification methodology" (i.e. a bunch of libraries), seems to be all the rage in hardware verification land.
如果不知道您的 DUV（正在验证的设备）或您拥有的 C 代码，这个问题就不容易回答。 您需要方法来刺激和检查您的设计，在这里您可能需要在事务级别（C 数据结构）与引脚级别之间进行转换。 SystemVerilog 接口或 SystemC 可能是一种方法。 我还没有使用过DPI/PLI接口。
要拥有“最先进的”测试平台，您应该考虑使用其中一种测试平台方法，即 VMM 或 OVM。 他们还将为您提供如何入门的文档。
The question is not so easy to answer without knowing your DUV (device under verification) or the C code you have. You need means to stimulate and check your design, here you probably need to translate from/to transaction level (C data structures) to/from pin level. SystemVerilog interfaces or SystemC may be an approach. I haven't used DPI/PLI interfaces yet.
To have a "state-of-the-art" testbench you should consider to use one of the testbench methodologies out there, namely VMM or OVM. They will also provide you with documentation how to get started.
听起来您应该使用 Mentor 或 Cadence 模拟器之类的工具，将 RTL 和 SystemC 代码组合在一个系统下。 当然不是免费的，但它们是实践中存在的解决方案。
您需要的结构上正确的解决方案是让 C 或 SystemC 调用 RTL，而不是相反。 这样做意味着将一些 RTL 模拟器与您的 C 程序或 SystemC 程序集成。 这当然是可行的，但却是一项相当艰巨的任务。
另外，我认为使用 SystemVerilog 很有意义。
Sounds like you should get a tool like Mentor's or Cadence's simulators that combine RTL and SystemC code under a single system. Not free, certainly, but they are the solution for that exists in practice.
The structurally correct solution you need is for the C or SystemC to call into the RTL, not the other way around. Doing this implies integrating some RTL simulator with your C program or SystemC program. It is certainly doable, but a pretty big undertaking.
Also, i think that using SystemVerilog makes a lot of sense.
我已经使用 SystemC 和 System Verilog/VMM 进行验证，答案是，这取决于情况。 当我在一家预算有限的初创公司试图推出他们的第一个 ASIC 时，SystemC 是一个自然的选择，因为它在我们的低预算模拟器上运行，而 SystemVerilog 则不能。 使用 SystemC，您不需要使用 PLI 或 DPI。 您实际上将 SystemC 模型实例化为测试平台中的组件，这很有趣。
然而，SystemC 是一个 C++ 库，没有非常直观的语法。 在尝试学习 SystemC 库之前，您应该具备良好的 C++ 背景。 除了 David Black 的《SystemC from the Ground Up》之外，现有的这方面书籍大多都很糟糕。
首先，据我所知，SystemC 自然是一种高级建模语言，而不是验证语言，并且没有人有预算购买真正的模拟器，而不再使用 SystemC 进行验证。 从一般职业发展的角度来看，如果您可以使用 System Verilog，我会使用它。 另外，您始终可以使用 DPI 连接到 C 模型进行输出检查，该模型仍然使用以 SV/VMM 编写的生成器、监视器和记分板。
I've used both for SystemC and System Verilog/VMM for verification, and the answer is, it depends. When I was with a startup that was on a shoestring budget trying to get their first ASIC out the door, SystemC was a natural choice because it ran on our low-budget simulator and SystemVerilog did not. With SystemC, you don't need to use the PLI or the DPI. You actually instantiate your SystemC model as a component in your testbench, which is interesting.
However, SystemC is a C++ library that does NOT have a very intuitive syntax. You should have a decent C++ background before attempting to learn the SystemC library. The books for this that are available mostly suck, except for "SystemC from the Ground Up" by David Black.
That begin said, from what I've seen, SystemC is naturally a high-level modeling language, not a verification language, and nobody with any budget to buy real simulators is using SystemC for verification anymore. From a general career development standpoint, I would use System Verilog if it is available to you. Plus, you can always use the DPI to interface to your C model for output checking, which still using generators, monitors and scoreboards written in SV/VMM.