如何在 Makefile 目标中使用 Bash 语法?
我经常发现 Bash 语法非常有用,例如 diff 中的进程替换<(排序文件1)<(排序文件2)
。
是否可以在 Makefile 中使用此类 Bash 命令? 我正在考虑这样的事情:
file-differences:
diff <(sort file1) <(sort file2) > $@
在我的 GNU Make 3.80 中,这将给出一个错误,因为它使用 sh
而不是 bash
来执行命令。
I often find Bash syntax very helpful, e.g. process substitution like in diff <(sort file1) <(sort file2)
.
Is it possible to use such Bash commands in a Makefile? I'm thinking of something like this:
file-differences:
diff <(sort file1) <(sort file2) > $@
In my GNU Make 3.80 this will give an error since it uses sh
instead of bash
to execute the commands.
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有一种方法可以做到这一点,而无需显式地将 SHELL 变量设置为指向 bash。 如果您有许多 makefile,这可能很有用,因为 SHELL 不会被后续 makefile 继承或从环境中获取。 您还需要确保编译您代码的任何人都以这种方式配置他们的系统。
如果您运行 sudo dpkg-reconfigure dash 并对提示回答“否”,您的系统将不会使用 dash 作为默认 shell。 然后它将指向 bash(至少在 Ubuntu 中)。 请注意,使用 dash 作为系统 shell 效率更高一些。
There is a way to do this without explicitly setting your SHELL variable to point to bash. This can be useful if you have many makefiles since SHELL isn't inherited by subsequent makefiles or taken from the environment. You also need to be sure that anyone who compiles your code configures their system this way.
If you run
sudo dpkg-reconfigure dash
and answer 'no' to the prompt, your system will not use dash as the default shell. It will then point to bash (at least in Ubuntu). Note that using dash as your system shell is a bit more efficient though.这不是问题的直接答案, makeit 是用 bash 语法进行有限的 Makefile 替换,它可以在某些情况下很有用(我是作者)
基本思想是在末尾有
while
循环脚本:https://asciinema.org/a/435159
It's not a direct answer to the question, makeit is limited Makefile replacement with bash syntax and it can be useful in some cases (I'm the author)
Basic idea is to have
while
loop in the end of the script:https://asciinema.org/a/435159
从 GNU Make 文档,
所以把 < code>SHELL := /bin/bash 位于你的 makefile 顶部,你应该可以开始了。
顺便说一句:您也可以对一个目标执行此操作,至少对于 GNU Make 来说是这样。 每个目标都可以有自己的变量分配,如下所示:
将打印:
有关更多详细信息,请参阅文档中的“特定于目标的变量值”。 该行可以位于 Makefile 中的任何位置,不必位于目标之前。
From the GNU Make documentation,
So put
SHELL := /bin/bash
at the top of your makefile, and you should be good to go.BTW: You can also do this for one target, at least for GNU Make. Each target can have its own variable assignments, like this:
That'll print:
See "Target-specific Variable Values" in the documentation for more details. That line can go anywhere in the Makefile, it doesn't have to be immediately before the target.
你可以直接调用
bash
,使用-c
标志:当然,你可能无法重定向到变量$@,但是当我尝试这样做时,我收到了
-bash: $@: ambigously redirect
作为错误消息,因此您可能需要在深入研究之前先研究一下(尽管我使用的是 bash 3.2.something,所以也许您的工作方式不同)。You can call
bash
directly, use the-c
flag:Of course, you may not be able to redirect to the variable $@, but when I tried to do this, I got
-bash: $@: ambiguous redirect
as an error message, so you may want to look into that before you get too into this (though I'm using bash 3.2.something, so maybe yours works differently).一种可行的方法是将其放在目标的第一行中:
One way that also works is putting it this way in the first line of the your target:
如果可移植性很重要,您可能不想依赖 Makefile 中的特定 shell。 并非所有环境都可以使用 bash。
If portability is important you may not want to depend on a specific shell in your Makefile. Not all environments have bash available.
您可以直接在 Makefile 中调用 bash,而不是使用默认 shell:
而不是:
You can call bash directly within your Makefile instead of using the default shell:
instead of: