您将如何处理这个数字逻辑系统中的特殊情况？
我将此数字逻辑图发布为答案< /a> 到另一个 stackoverflow 问题。 它描述了一个逻辑系统，该系统将用 Verilog 或 VHDL 编码并最终在 FPGA 中实现。
替代文本 http://img145.imageshack.us/img145/5125/bitshifterlogicdiagramkn7.jpg< /a>
图中的编号框代表字段中的位。 每个字段都有K位，并且当前和掩码的位将由计算机系统提供（使用锁存寄存器或等效物）。 next 中的位将被读回同一计算机系统。
只要 mask 字段中至少设置了一位，并且 current 位字段中恰好设置了一位，我发布的解决方案就可以工作。 这个想法是，在计算机系统执行某些任务（在原始问题中是调度操作）后，下一个位字段将成为当前位字段。
所以，我的问题是这样的： 您将如何修改此系统，以便它正确处理当前位字段全为零（未设置位）的特殊情况？就目前情况而言，如果所有位都在current 为零，无论 mask 中的位设置为何，输出也将为零。
理想情况下，如果current全为零，则应在next中设置mask中的最低设置位。 系统还应保持可扩展至任意位数 (K)，而无需添加指数级更多的逻辑门。 最初问题的精神是提出一个可以直接实现任意位数的解决方案。
另请参阅：此 stackoverflow 问题
I posted this digital logic diagram as an answer to another stackoverflow question. It describes a logic system which will be coded in Verilog or VHDL and eventually implemented in an FPGA.
alt text http://img145.imageshack.us/img145/5125/bitshifterlogicdiagramkn7.jpg
The numbered boxes in the diagram represent bits in a field. Each field has K bits, and the bits for current and mask will be provided by a computer system (using a latched register or equivalent). The bits in next will be read back into that same computer system.
The solution that I posted works as long as there is at least one bit set in the mask field, and there is exactly one bit set in the current bit field. The idea is that the next bit field will become the current bit field after the computer system has performed some task (a scheduling operation, in the original question).
So, my question is this:
How would you modify this system so that it properly handles the special case where the current bit field is all zero (no bits set)? As it stands, if all bits in current are zero, the output will also be zero, no matter what the bits in mask are set to.
Ideally, if current is all zeroes, the lowest set bit in mask should be set in next. The system should also still remain scalable to any number of bits (K) without having to add exponentially more logic gates. The spirit of the original question was to come up with a solution that would be straightforward to implement for any number of bits.
See also: this stackoverflow question
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对我来说，我会告诉 FPGA 用户他们必须在进入时将其中一位设置为 1。
但是，如果这不是您首选的解决方案，那么将所有当前输入最初预馈入一个大或非门（以便仅当所有输入均为假时输出为真）的想法有什么问题。 所有电流线也继续通过它们的与门，除了 Current[1] 在进入它的与门之前与我们的或非门的输出进行或运算
这样，电流[1]进入与门将是真实的，如果所有电流都是假的。
请记住，我了解布尔代数，但我从未使用过原始硬件 - 我猜您需要将所有输入信号缓冲到与门中以确保正确的时序，但我怀疑您会比I.
保留下图以防 SO 修复其代码/预块 - 最新的 SO 更新似乎已将它们塞满（使它们成比例，而不是固定宽度的字体）。 无论如何，eJames 的图表更好。
这是我的图表，比你的稍微不那么优雅:-)：
For me, I would tell the user of the FPGA that they must have one of the bits set to 1 on entry.
However, if that's not your preferred solution, what's wrong with the idea of pre-feeding all the Current inputs initially into a big NOR gate (so that the output is true only when all inputs are false). All Current lines also continue through to their AND gates with the exception that Current[1] is OR'ed with the output of our NOR gate before entering it's AND gate
That way, Current[1] would be true entering the AND gate, if all Currents are false.
Keep in mind that I understand boolean algebra but I've never worked on raw hardware - I'm guessing you'll need to buffer all the input signals into the AND gates to ensure correct timing but i suspect you'll know that better than I.
The following diagram is left in in case SO fixes its code/pre blocks - the latest SO update seems to have stuffed them up (leaving them proportional, not fixed-width, font). Anyway, eJames' graphical diagram is better.
Here's my diagram, slightly less elegant than yours :-):
+-------------------+ | | | +---- | Current[1]-----+------\ \ | |NOR|o--+ | Current[2-k]---+------/ / | | | +---- | | | +\ /+ | | \_/ | +---+ | OR | \ /Buffer \ / + --- | | +---+ +---+ |2-k| | 1 | <- These signals feed +---+ +---+ into your AND gates.