系统verilog中的打包向量与未打包向量
查看我在 System Verilog 中维护的一些代码，我看到一些信号的定义如下：
node [range_hi:range_lo]x;
以及其他信号的定义如下：
node y[range_hi:range_lo];
我知道 x 被定义为打包，而 y 被定义为未打包。 但是，我不知道这意味着什么。
System Verilog 中打包向量和未打包向量有什么区别？
编辑：回应@Empi的回答，为什么用SV编写的硬件设计师应该关心数组的内部表示？ 有没有什么时候我不应该或不能使用打包信号？
Looking at some code I'm maintaining in System Verilog I see some signals that are defined like this:
node [range_hi:range_lo]x;
and others that are defined like this:
node y[range_hi:range_lo];
I understand that x is defined as packed, while y is defined as unpacked. However, I have no idea what that means.
What is the difference between packed and unpacked vectors in System Verilog?
Edit: Responding to @Empi's answer, why should a hardware designer who's writing in SV care about the internal representation of the array? Are there any times when I shouldn't or can't use packed signals?
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本文提供了有关此问题的更多详细信息：
http://electricsofts.com/systemverilog/arrays.html，尤其是第 5.2 节。
This article gives more details about this issue:
http://electrosofts.com/systemverilog/arrays.html, especially section 5.2.
在了解打包和解包数组到底是什么之前，我们还可以看看如何仅通过它们的声明来知道哪个数组是什么。
压缩数组有一个对象名称，位于大小声明之后。 例如：
其中
a是细分为 3 个 7 位子字段的 28 位向量。解压数组的对象名称位于大小声明之前。 例如：
其中
b是 3 位宽的向量。打包数组会占用内存，而未打包数组则不会。
您也可以像这样访问/声明未打包的数组。
您也可以混合打包和未打包的数组来创建多维数组。 例如：
它创建一个4（即4*8）字节的数组，深度为3。
Before knowing what exactly packed and unpacked arrays are, lets also see how you can know which array is what, just by their declaration.
Packed arrays have an object name which comes after the size declaration. For example:
where
ais a 28-bit vector subdivided into 3 7-bit subfields.Unpacked arrays have an object name which comes before the size declaration. For example:
where
bis a 3-bit wide vector.Packed arrays make memory whereas Unpacked don't.
You can access/declare unpacked arrays like this also
You can mix both packed and unpacked array to make a multidimensional array. For example:
It makes an array of 4 (i.e. 4*8) bytes with depth of 3.
当我们写入 [3:0][7:0]A[4:0] 时，压缩数组主要用于有效的内存使用，这意味着在 32 位内存位置中，每个 8 位的 4 个切片被打包形成一个 32 位。 右侧的值表示有 5 个这样的切片。
Packed array are mainly used for effective memory usage when we are writing a [3:0][7:0]A[4:0] which means in 32 bit memory locations 4slices each of 8 bit are packed to form a 32 bit. The right side value means there are 5 such slices are there.
位[3:0] a-> 压缩数组打包数组可以用作完整数组 (
a='d1) 或仅数组的一部分 (a[0]='b1)bit a [3:0]-> 解包数组解压后的数组不能用作
a[0]='b1，它必须用作完整的a={8{'b1}}bit[3:0] a-> packed arrayThe packed array can be used as a full array (
a='d1) or just part of an array (a[0]='b1)bit a [3:0]-> unpacked arrayThe unpacked array cannot be used as
a[0]='b1, it has to be used as fulla={8{'b1}}验证学院给出了很好的解释。
n向量的压缩数组可以想象为单行 n 列的数组。而
“n”向量和“m”的解压缩数组解压缩维度可以想象为 >n 列 m 行的矩阵/二维数组。A good explanation is given at verification academy.
A packed array of
nvectorscan be imagined as an array of single row and n columns.Whereas an unpacked array of
"n" vectors and "m"unpacked dimensionscan be imagined as amatrix/2D arrayof n columns and m rows.与打包数组相比，未打包数组将为您提供更多编译时错误检查。
由于这个原因，我在模块的端口定义上看到了未打包的数组。 如果信号的维度与解包数组的端口不完全相同，编译器将出错。 对于打包数组，它通常会继续并尽可能地连接事物，而不会发出错误。
Unpacked arrays will give you more compile time error checking than packed arrays.
I see unpacked arrays on the port definitions of modules for this reason. The compiler will error if the dimensions of the signal are not exactly the same as the port with unpacked arrays. With packed arrays it will normally just go ahead and wire things the best it can, not issuing an error.
位a [3:0] -> 解压数组 解压数组不能用作 a[0]='b1，它必须用作完整的 a={8{'b1}}
---> 在上面的语句中 a[0] ='b1; 将适用于解压数组，它不适用于 unpkd arry[例如逻辑 unpkd [8];] 的某些部分，如 unpkd = 5'h7; 分配同样适用于 pkd 数组
--> 解开PKD = 解开PKD +2； 不适用于 unpkd 将适用于 pkd
bit a [3:0] -> unpacked array The unpacked array cannot be used as a[0]='b1, it has to be used as full a={8{'b1}}
---> in above statement a[0] ='b1; will work for unpacked array , it won't work where some portion of the unpkd arry[eg logic unpkd [8];] like unpkd = 5'h7; assignment same will work for pkd array
--> unpkd = unpkd +2; won't wok for unpkd will work for pkd