如何禁用 PowerPC 处理器上的处理器缓存？
在我们的嵌入式系统（使用 PowerPC 处理器）中，我们想要禁用处理器缓存。 我们需要采取什么步骤？
为了澄清一点，所讨论的应用程序必须具有尽可能恒定的执行速度。 执行相同代码路径时的变化是不可接受的。 这就是关闭缓存的原因。
In our embedded system (using a PowerPC processor), we want to disable the processor cache. What steps do we need to take?
To clarify a bit, the application in question must have as constant a speed of execution as we can make it.
Variability in executing the same code path is not acceptable. This is the reason to turn off the cache.
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我有点晚了这个问题，而且自从我在 PPC 上完成所有低级处理器初始化代码以来已经有一段时间了，但我似乎记得缓存和缓存。 MMU 耦合非常紧密（必须启用一个才能启用另一个），我认为在 MMU 页表中，您可以定义可缓存属性。
所以我的观点是：如果有某个代码子集必须在确定的时间内运行，也许您将该代码（通过链接器命令文件）定位在页表中定义为不可缓存的内存区域中？ 这样，所有可以/应该从缓存中受益的代码都会受益，而（希望）不应该受益的代码子集则不会。
无论如何我都会这样处理它，这样以后，如果你想为系统的一部分启用缓存，你只需要翻转MMU页表中的一些位，而不是（重新）编写初始化代码设置所有页表和页表 缓存。
I'm kind of late to the question, and also it's been a while since I did all the low-level processor init code on PPCs, but I seem to remember the cache & MMU being pretty tightly coupled (one had to be enabled to enable the other) and I think in the MMU page tables, you could define the cacheable attribute.
So my point is this: if there's a certain subset of code that must run in deterministic time, maybe you locate that code (via a linker command file) in a region of memory that is defined as non-cacheable in the page tables? That way all the code that can/should benefit from the cache does, and the (hopefully) subset of code that shouldn't, doesn't.
I'd handle it this way anyway, so that later, if you want to enable caching for part of the system, you just need to flip a few bits in the MMU page tables, instead of (re-)writing the init code to set up all the page tables & caching.
它是什么样的PPC核心？ 不同供应商的不同内核之间的缓存控制非常不同......而且，禁用缓存通常被认为对机器来说是一件非常糟糕的事情。 性能变得极其缓慢，以至于使用旧的 8 位处理器也能达到同样的效果（有点夸张）。 一些 ARM 变体具有 TCM（紧耦合内存），可以代替缓存工作，但我不知道有任何 PPC 变体具有该功能。
也许更好的解决方案是保持 1 级缓存处于活动状态，并使用片上 L2 缓存作为静态映射 RAM？ 这至少在现代 PowerQUICC 设备上很常见。
What kind of PPC core is it? The cache control is very different between different cores from different vendors... also, disabling the cache is in general considered a really bad thing to do to the machine. Performance becomes so crawlingly slow that you would do as well with an old 8-bit processor (exaggerating a bit). Some ARM variants have TCMs, tightly-coupled memories, that work instead of caches, but I am not aware of any PPC variant with that facility.
Maybe a better solution is to keep Level 1 caches active, and use the on-chip L2 caches as statically mapped RAM instead? That is common on modern PowerQUICC devices, at least.
来自 E600 参考手册：
HID0 专用寄存器包含多个位，用于使指令和数据缓存无效、禁用和锁定。
您应该使用 HID0[DCE] = 0 来禁用数据缓存。
您应该使用 HID0[ICE] = 0 来禁用指令缓存。
请注意，加电时，两个缓存均被禁用。
您需要用汇编代码编写它。
From the E600 reference manual:
The HID0 special-purpose register contains several bits that invalidate, disable, and lock the instruction and data caches.
You should use HID0[DCE] = 0 to disable the data cache.
You should use HID0[ICE] = 0 to disable the instruction cache.
Note that at power up, both caches are disabled.
You will need to write this in assembly code.
也许您不想全局禁用缓存，而只想针对特定地址范围禁用它？
在某些处理器上，您可以为地址范围配置 TLB（转换后备缓冲区）条目，以便每个范围都可以启用或禁用缓存。 通过这种方式，您可以禁用内存映射 I/O 的缓存，但仍保留主 RAM 块的缓存。
我唯一使用过的 PowerPC 是 PowerPC 440EP（来自 IBM，然后是 AMCC），所以我不知道是否所有 PowerPC 都以相同的方式工作。
Perhaps you don't want to globally disable cache, you only want to disable it for a particular address range?
On some processors you can configure TLB (translation lookaside buffer) entries for address ranges such that each range could have caching enabled or disabled. This way you can disable caching for memory mapped I/O, and still leave caching on for the main block of RAM.
The only PowerPC I've done this on was a PowerPC 440EP (from IBM, then AMCC), so I don't know if all PowerPCs work the same way.
关闭缓存对您没有任何好处。 你的执行速度将会下降一个数量级。 您永远不会发布这样的系统，因此它在这些条件下的性能并不重要。
要获得稳定的执行速度，请考虑以下方法之一：
1) 锁定部分或全部缓存。 目前 Freescale、IBM 和 AMCC 的所有 PowerPC 芯片都提供此功能。
2) 如果是具有二级缓存的飞思卡尔芯片，请考虑将该缓存的一部分映射为片上内存。
Turning off the cache will do you no good at all. Your execution speed will drop by an order of magnitude. You would never ship a system like this, so its performance under these conditions is of no interest.
To achieve a steady execution speed, consider one of these approaches:
1) Lock some or all of the cache. All current PowerPC chips from Freescale, IBM, and AMCC offer this feature.
2) If it's a Freescale chip with L2 cache, consider mapping part of that cache as on-chip memory.