在哪里可以找到*所有* MIPS 指令的描述

发布于 2024-07-05 09:35:55 字数 356 浏览 10 评论 0原文

有谁知道一个网站,我可以在其中找到 32 位 MIPS 指令/操作码的列表,具有以下功能:

  • 清楚地区分真正的操作码和汇编语言宏(伪指令)
  • 描述指令行为,包括取决于不同条件的差异特权级别。
  • 指示指令在哪个指令集修订版中引入/修订(例如,MIPS I、MIPS II、MIPS32 等)。
  • 包括特权指令,例如系统调用。

我知道有许多网站记录了指令集的“部分”,主要用于教学目的。 他们倾向于省略或仅部分描述浮点和特权指令。

如果您想知道,我正在查看 MIPS 处理器子集的 Verilog 代码,并试图弄清楚它在多大程度上符合任何真正的 MIPS 处理器的指令集!

Does anyone know of a web site where I can find a list of 32-bit MIPS instructions/opcodes, with the following features:

  • Clearly distinguishes between real opcodes and assembly-language macros (pseudo-instructions)
  • Describes the instruction behavior including differences depending on privilege level.
  • Indicates in which instruction set revision the instruction was introduced/revised (e.g. MIPS I, MIPS II, MIPS32, etc.)
  • Includes privileged instructions such as syscall.

I am aware of numerous web sites which document "part of" the instruction set, mostly for teaching purposes. They tend to leave out or only partially describe floating-point and privileged instructions.

In case you're wondering, I'm looking at Verilog code for a MIPS processor subset, and trying to figure out exactly to what extent it complies with the instruction sets of any real MIPS processors!

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衣神在巴黎 2024-07-12 09:35:55

好吧,我发现了一些东西!

MIPS 提供了一套“MIPS 32 参考手册”,其中涉及最新的标准化指令集 (MIPS32v2):这里

这些几乎包括所有内容,除了有关指令源自哪个版本的信息:-(

稍等一下...

康奈尔大学的此类网站包含看似相同手册的链接,但实际上是旧版本,以及第 2 卷 实际上包含有关首次引入指令的时间的信息!

为什么 MIPS 会从修订的文档中删除此信息?在修订历史记录中似乎没有任何解释。

Okay, I found something!

MIPS offers a set of "MIPS 32 reference manuals" which refer to the latest, standardized instruction set (MIPS32v2): here

These include just about everything, except the information about which version the instructions originated in :-(

WAIT A SEC...

This class website at Cornell includes links to what appears to be the same manual, but is in fact an older version of it, and volume 2 of that older version does in fact include information about when the instructions where first introduced. Woohoo!

Why would MIPS remove this information from the revised documentation? There doesn't seem to be any explanation in the revision history.

断念 2024-07-12 09:35:55

我只能部分回答这个问题:我建议 查看 MIPS Run多米尼克·斯威特曼(Dominic Sweetman),如果你还没有提到的话。 我有这本书的第一版,现在是第二版。

  • 表 8.2 列出了每个操作码和预期行为,区分汇编器宏并列出它们分解为的指令。 不幸的是,它不区分用户模式和内核模式。
  • 表 8.6 列出了引入每条指令的 ISA 级别,包括
  • 表中存在的像 LSI MiniRISC 系统调用这样的模糊变体,尽管缺乏太多描述。

第一版提到了内核。 主管和用户权限级别,但没有讨论每个权限级别允许哪些操作。 不知道第二版有哪些改动。

I can only partially answer the question: I'd recommend See MIPS Run by Dominic Sweetman, if you're not already referring to it. I have the first edition of the book, the second edition is now current.


  • table 8.2 lists each opcode and expected behavior, differentiating assembler macros and listing the instructions they decompose to. Unfortunately it does not differentiate user vs kernel mode.

  • table 8.6 lists the ISA level where each instruction was introduced, including obscure variants like the LSI MiniRISC

  • syscall is present in the table, though lacking much description

The first edition mentions the kernel. supervisor, and user privilege levels but does not discuss what operations are allowed in each. I do not know what changes were made in the second edition.

马蹄踏│碎落叶 2024-07-12 09:35:55

不包括指令描述,但 GNU 汇编器的源代码可能尽可能详细地说明了哪些指令在哪些特定 CPU 上可用。

获取 binutils 并查看 opcodes/mips-*.c

Doesn't include instruction descriptions, but the source of the GNU assembler is probably as detailed as you can get regarding what instructions are available on what specific CPUs.

Get binutils and look at opcodes/mips-*.c

葬花如无物 2024-07-12 09:35:55

当前指令集参考手册可在线免费获取:面向程序员的 MIPS® 架构
第 II-A 卷:MIPS32® 指令
设置手动
。 该链接是修订版 6.06
2016 年 12 月 15 日。(即它记录了 MIPS32 Release 6)。

它记录了所有用户和主管/内核模式指令以及所有浮点指令,详细记录了它们的机器代码编码,并通过操作部分显示了它们的作用。 它仍然记录了 MIPS32 第 6 版中删除的所有指令。(MIPS32 第 6 版还移动了很多操作码,并且有详细记录)。


请参阅https://www.mips.com/products/architectures/mips32/获取最新版本。 mips.com 有一个“经典内核”部分,但这似乎仍然只能追溯到 MIPS32,而不是历史的东西。


balc 的“可用性和兼容性”部分示例(分支和链路紧凑:无分支延迟槽,GRP31 是隐式目标,为 offset<< 释放 26 位) 2):

此指令由版本 6 引入并要求。
第 6 版指令 BALC 占用与第 6 版之前版本相同的编码
指令SWC2SWC2 指令已移至 COP2
MIPS Release 6 中的主要操作码

或用于 LDXC1 fd, index(base) (加载双字索引到浮点)

该指令已在版本 6 中删除。
自 MIPS64 Release 1 以来的所有 MIPS64 版本中都需要。在 MIPS32 Release 1 中不可用。在 MIPS32 Release 1 中需要。
MIPS32 Release 2 以及 MIPS32 的所有后续版本。 需要时,只要 FPU 存在就需要,
无论是 32 位还是 64 位 FPU,无论是 32 位还是 64 位 FP 寄存器模式(FIRF64=0 或 1,StatusFR=0 或 1)。


对于历史资料,我找到了 MIPS IV 指令集
版本3.2
1995 年 9 月
cmu.edu 网页上。 它列出了指令引入的时间,例如 MIPS I 用于 div、MIPS III 用于 dmult 和其他 64 位指令、MIPS II 用于 ll / sc


关于每条指令效果的伪代码快速参考https://inst.eecs.berkeley.edu/~cs61c/resources/MIPS_help.html。 它不包括编码细节,但准确地描述了分支和跳转指令对程序计数器的影响。 (这有点棘手:它们相对于或绝对于分支延迟槽。)

不过,即使对于 MIPS I 整数指令来说,它也不完整:它缺少未对齐加载帮助器指令 LWL 和 LWR 以及相应的 SWL/R它也不包含任何 FP 内容或后来的 MIPS 指令,例如 mul(仅 mult)。 我不知道还缺少什么; 我没有将其与完整列表交叉引用。

上面链接的 MIPS-IV 手册确认了 lwl/lwr 在 MIPS I 中可用(并记录了加载延迟槽限制适用于它们)。

The current instruction-set reference manual is free online: MIPS® Architecture for Programmers
Volume II-A: The MIPS32® Instruction
Set Manual
. That link is Revision 6.06
December 15, 2016. (i.e. it documents MIPS32 Release 6).

It documents all user and supervisor/kernel mode instructions, and all floating-point, in full detail including their machine-code encoding, and with an Operation section that shows what they do. It still documents all the instructions that were removed in MIPS32 release 6. (MIPS32 Release 6 also moved around a lot of opcodes, and this is well documented).


See https://www.mips.com/products/architectures/mips32/ for the latest version. mips.com has a section for "classic cores", but that still appears to only go back to MIPS32, not historical stuff.


Sample of the "availability and compatibility" section for balc (Branch and Link Compact: no branch-delay slot, and GRP31 is the implicit destination, freeing up 26 bits for an offset<<2):

This instruction is introduced by and required as of Release 6.
Release 6 instruction BALC occupies the same encoding as pre-Release 6
instruction SWC2. The SWC2 instruction has been moved to the COP2
major opcode in MIPS Release 6

Or for LDXC1 fd, index(base) (Load Doubleword Indexed to Floating Point)

This instruction has been removed in Release 6.
Required in all versions of MIPS64 since MIPS64 Release 1. Not available in MIPS32 Release 1. Required in
MIPS32 Release 2 and all subsequent versions of MIPS32. When required, required whenever FPU is present,
whether a 32-bit or 64-bit FPU, whether in 32-bit or 64-bit FP Register Mode (FIRF64=0 or 1, StatusFR=0 or 1).


For historical stuff, I found the MIPS IV Instruction Set
Revision 3.2
September, 1995
on a cmu.edu web page. It lists when instructions were introduced, e.g. MIPS I for div, MIPS III for dmult and other 64-bit instructions, MIPS II for ll / sc.


A good quick-reference with pseudocode for the effect of each instruction is https://inst.eecs.berkeley.edu/~cs61c/resources/MIPS_help.html. It doesn't include encoding details, but does accurately describe the effect of branch and jump instructions on the program counter. (Which is somewhat tricky: they're relative or section-absolute to the branch-delay slot.)

It's not complete even for MIPS I integer instructions, though: it's missing the unaligned-load helper instructions LWL and LWR and corresponding SWL/R stores which were present in MIPS I. It also doesn't include any FP stuff, or later MIPS instructions like mul (only mult). I don't know what else might be missing; I didn't cross reference it against a complete list.

The MIPS-IV manual linked above confirms that lwl/lwr were available in MIPS I (and documents that the load delay slot restriction applies to them).

爱已欠费 2024-07-12 09:35:55

这个 网站 (archive.org) 描述了大部分 MIPS 指令集及其编码。 但它并不完整:至少缺少 nor ,也许还缺少其他东西。

有关每条指令效果的伪代码的一个很好的快速参考是 https:/ /inst.eecs.berkeley.edu/~cs61c/resources/MIPS_help.html。 它不包括编码细节。

MIPS网站还提供有关各种内核的技术文档。
例如,我下载了 MIPS 4KE 内核的手册(文档#MD00103)“MIPS32® 4KE™ 处理器内核系列软件用户手册”,第 10 章包含指令集的详细说明。
请注意,您必须注册才能访问这些文档。

This web site (archive.org) describes most of the MIPS instruction set and their encoding. It's not complete, though: missing at least nor and maybe other things.

A good quick-reference with pseudocode for the effect of each instruction is https://inst.eecs.berkeley.edu/~cs61c/resources/MIPS_help.html. It doesn't include encoding details.

The MIPS web site also has technical documents about the various cores.
For example, I downloaded the manual for the MIPS 4KE core (document #MD00103) "MIPS32® 4KE™ Processor Core Family Software User’s Manual" and chapter 10 contains a detailed description of the Instruction Set.
Note that you have to register to access the documents.

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