Verilog 中 4 对 1 函数的高效综合

发布于 2024-07-04 21:46:37 字数 383 浏览 14 评论 0原文

我需要在 Veriog 中实现 4 对 1 函数。输入为 4 位，即 0-15 之间的数字。输出是单个位，0 或 1。每个输入给出不同的输出，并且从输入到输出的映射是已知的，但输入和输出本身未知。我希望 vcs 能够成功优化代码，并使其尽可能短/简洁。到目前为止我的解决方案：

wire [3:0] a;
wire b;
wire [15:0] c;

assign c = 16'b0100110010111010; //for example but could be any constant
assign b = c[a];

必须声明 c 很丑陋，我不知道 vcs 是否会识别那里的 K-map。这是否与 case 语句或连接范式的作业一样有效？

原文

I need to implement a 4-to-1 function in Veriog. The input is 4 bits, a number from 0-15. The output is a single bit, 0 or 1. Each input gives a different output and the mapping from inputs to outputs is known, but the inputs and outputs themselves are not. I want vcs to successfully optimizing the code and also have it be as short/neat as possible. My solution so far:

wire [3:0] a;
wire b;
wire [15:0] c;

assign c = 16'b0100110010111010; //for example but could be any constant
assign b = c[a];

Having to declare c is ugly and I don't know if vcs will recognize the K-map there. Will this work as well as a case statement or an assignment in conjunctive normal form?

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墨落成白 2024-07-11 21:46:37

显然我使用的是一个糟糕的合成工具。 :-) 我刚刚综合了两个版本（只是使用基于线延迟扇出的模型的模块），问题中的索引版本给出了比 case 语句更好的时序和面积结果。使用 Synopsys DC Z-2007.03-SP。

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半夏半凉 2024-07-11 21:46:37

对于这样的事情，RTL 清晰度远远胜过一切。 SystemVerilog 有特殊的always 块指令，以明确该块何时应综合为组合逻辑、锁存器或触发器（如果您编写的 RTL 与该指令相冲突，您的综合工具应抛出错误（例如，不包括另请注意，该工具可能会用最有效的硬件编码（最小化整个设计面积的编码）替换您拥有的任何编码，除非编码本身传播到引脚。。

这个建议也是一般性的，让你的代码易于人类理解，并且对于综合工具来说也可能更容易理解，这使得它能够更有效地从字面上带来 如果您愿意，您还可以使用三元运算符进行数千人年的算法研究，

但我更喜欢以下内容：

always_comb //or "always @*" if you don't have an SV-enabled tool flow
begin 
  case(a)
  begin
    4'b0000: b = 1'b0;
    4'b0001: b = 1'b1;
    ...
    4'b1111: b = 1'b0;
    //If you don't specify a "default" clause, your synthesis tool
    //Should scream at you if you didn't specify all cases,
    //Which is a good thing (tm)
  endcase //a
end //always

For things like this, RTL clarity trumps all by a wide margin. SystemVerilog has special always block directives to make it clear when the block should synthesize to combinational logic, latches, or flops (and your synthesis tool should throw an error if you've written RTL that conflicts with that (e.g. not including all signals in the sensitivity list of an always block). Also be aware that the tool will probably replace whatever encoding you have with the most hardware-efficient encoding (the one that minimizes the area of your total design), unless the encoding itself propagates out to the pins of your top-level module.

This advice goes in general, as well. Make your code easy to understand by humans, and it will probably be more understandable to the synthesis tool as well, which allows it to more effectively bring literally thousands of man-years of algorithms research to bear on your RTL.

You can also code it using ternary operators if you like, but i'd prefer something like:

always_comb //or "always @*" if you don't have an SV-enabled tool flow
begin 
  case(a)
  begin
    4'b0000: b = 1'b0;
    4'b0001: b = 1'b1;
    ...
    4'b1111: b = 1'b0;
    //If you don't specify a "default" clause, your synthesis tool
    //Should scream at you if you didn't specify all cases,
    //Which is a good thing (tm)
  endcase //a
end //always

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