lex/flex and yacc/bison provide easy-to-use, well-understood lexer- and parser-generators, and I'd really recommend doing something like that as opposed to doing it procedurally in e.g. Perl. Regular expressions are powerful stuff for ripping apart strings with relatively-, but not totally-fixed structure. With any real programming language, the size of your state machine gets to be simply unmanageable with anything short of a Real Lexer/Parser (tm). Imagine dealing with all possible interleavings of keywords, identifiers, operators, extraneous parentheses, extraneous semicolons, and comments that are allowed in something like Verilog AMS, with regular expressions and procedural code alone.
There's no denying that there's a substantial learning curve there, but writing a grammar that you can use for flex and bison, and doing something useful on the syntax tree that comes out of bison, will be a much better use of your time than writing a ton of special-case string-processing code that's more naturally dealt with using a syntax-tree in the first place. Also, what you learn writing it this way will truly broaden your skillset in ways that writing a bunch of hacky Perl code just won't, so if you have the means, I highly recommend it ;-)
Also, if you're lazy, check out the Eclipse plugins that do syntax highlighting and basic refactoring for Verilog and VHDL. They're in an incredibly primitive state, last I checked, but they may have some of the code you're looking for, or at least a baseline piece of code to look at to better inform your approach in rolling your own.
Don't underestimate the amount of work that goes into a linter. Parsing is the easy part because you have tools (bison, flex, ANTLR/PCCTS) to automate much of it.
But once you have a parse, then what? You must build a semantic tree for the design. Depending on how complicated your inputs are, you must elaborate the Verilog-AMS design (i.e. resolving parameters, unrolling generates, etc. If you use those features). And only then can you try to implement rules.
I'd seriously consider other possible solutions before writing a linter, unless the number of users and potential time savings thereby justify the development time.
I've written a couple verilog parsers and I would suggest PCCTS/ANTLR if your favorite programming language is C/C++/Java. There is a PCCTS/ANTLR Verilog grammar that you can start with. My favorite parser generator is Zebu which is based on Common Lisp.
Of course the big job is to specify all the linting rules. It makes sense to make some kind of language to specify the linting rules as well.
yacc/bison definitely gives you a leg up, since good linting would require parsing the program. Regex (true regex, at least) might cover trivial cases, but it is easy to write code that the regexes don't match but are still bad style.
ANTLR looks to be an alternative path to the more common (OK I heard about them before) YACC/BISON approach, which it turns out also commonly use LEX/FLEX as a front end.
a Quick read of the FLEX man page kind of make me think It could be the framework for that regex type of idea..
Ok.. I'll let this stew a little longer, then see how quickly I can build a prototype parser in one or the other.
发布评论
评论（7）
lex/flex 和 yacc/bison 提供了易于使用、易于理解的词法分析器和解析器生成器，我真的建议您这样做，而不是在 Perl 等程序中按程序进行。 正则表达式是一种强大的东西，可以分解具有相对但不完全固定结构的字符串。 对于任何真正的编程语言，如果没有 Real Lexer/Parser (tm)，状态机的大小就会变得难以管理。 想象一下，仅使用正则表达式和程序代码来处理 Verilog AMS 等中允许的所有可能的关键字、标识符、运算符、无关括号、无关分号和注释的交错。
不可否认，那里有一个很大的学习曲线，但是编写一个可用于 flex 和 bison 的语法，并在 bison 产生的语法树上做一些有用的事情，将比编写一个语法更好地利用你的时间。大量特殊情况的字符串处理代码，首先使用语法树更自然地处理这些代码。 另外，通过这种方式编写的内容将真正拓宽您的技能，而编写一堆破烂的 Perl 代码则无法做到这一点，所以如果您有办法，我强烈推荐它;-)
另外，如果您很懒的话，查看为 Verilog 和 VHDL 进行语法突出显示和基本重构的 Eclipse 插件。 我上次检查时，它们处于令人难以置信的原始状态，但它们可能有您正在寻找的一些代码，或者至少有一段基线代码可供查看，以便更好地告知您自己的方法。
lex/flex and yacc/bison provide easy-to-use, well-understood lexer- and parser-generators, and I'd really recommend doing something like that as opposed to doing it procedurally in e.g. Perl. Regular expressions are powerful stuff for ripping apart strings with relatively-, but not totally-fixed structure. With any real programming language, the size of your state machine gets to be simply unmanageable with anything short of a Real Lexer/Parser (tm). Imagine dealing with all possible interleavings of keywords, identifiers, operators, extraneous parentheses, extraneous semicolons, and comments that are allowed in something like Verilog AMS, with regular expressions and procedural code alone.
There's no denying that there's a substantial learning curve there, but writing a grammar that you can use for flex and bison, and doing something useful on the syntax tree that comes out of bison, will be a much better use of your time than writing a ton of special-case string-processing code that's more naturally dealt with using a syntax-tree in the first place. Also, what you learn writing it this way will truly broaden your skillset in ways that writing a bunch of hacky Perl code just won't, so if you have the means, I highly recommend it ;-)
Also, if you're lazy, check out the Eclipse plugins that do syntax highlighting and basic refactoring for Verilog and VHDL. They're in an incredibly primitive state, last I checked, but they may have some of the code you're looking for, or at least a baseline piece of code to look at to better inform your approach in rolling your own.
不要低估 linter 的工作量。 解析是很容易的部分，因为您有工具（bison、flex、ANTLR/PCCTS）来自动化其中的大部分内容。
但是一旦你有了解析，然后呢？ 您必须为设计构建语义树。 根据输入的复杂程度，您必须详细阐述 Verilog-AMS 设计（即解析参数、展开生成等。如果您使用这些功能）。 只有这样你才能尝试执行规则。
在编写 linter 之前，我会认真考虑其他可能的解决方案，除非用户数量和潜在的时间节省足以证明开发时间是合理的。
Don't underestimate the amount of work that goes into a linter. Parsing is the easy part because you have tools (bison, flex, ANTLR/PCCTS) to automate much of it.
But once you have a parse, then what? You must build a semantic tree for the design. Depending on how complicated your inputs are, you must elaborate the Verilog-AMS design (i.e. resolving parameters, unrolling generates, etc. If you use those features). And only then can you try to implement rules.
I'd seriously consider other possible solutions before writing a linter, unless the number of users and potential time savings thereby justify the development time.
我已经编写了几个 verilog 解析器，如果您最喜欢的编程语言是 C/C++/Java，我建议使用 PCCTS/ANTLR。 您可以从 PCCTS/ANTLR Verilog 语法开始。 我最喜欢的解析器生成器是 Zebu，它基于 Common Lisp。
当然，最重要的工作是指定所有的 linting 规则。 使用某种语言来指定 linting 规则也是有意义的。
I've written a couple verilog parsers and I would suggest PCCTS/ANTLR if your favorite programming language is C/C++/Java. There is a PCCTS/ANTLR Verilog grammar that you can start with. My favorite parser generator is Zebu which is based on Common Lisp.
Of course the big job is to specify all the linting rules. It makes sense to make some kind of language to specify the linting rules as well.
在试图找到我的答案时，我在 ANTLR 上找到了这个 - 可能有用
In trying to find my answer, I found this on ANTLR - might be of use
如果您使用 Java（因此使用 IDEA），IDE 的自定义语言的扩展 可能有用
If you use Java at all (and thus IDEA), the IDE's extensions for custom languages might be of use
yacc/bison绝对可以为您提供帮助，因为良好的 linting 需要解析程序。 正则表达式（至少是真正的正则表达式）可能涵盖一些琐碎的情况，但很容易编写正则表达式不匹配但仍然是糟糕风格的代码。yacc/bisondefinitely gives you a leg up, since good linting would require parsing the program. Regex (true regex, at least) might cover trivial cases, but it is easy to write code that the regexes don't match but are still bad style.ANTLR 看起来是更常见的（好吧，我之前听说过它们）YACC/BISON 方法的替代路径，事实证明，YACC/BISON 方法也通常使用 LEX/FLEX 作为前端。
快速阅读 FLEX 手册页让我觉得它可能是正则表达式类型的想法的框架..
好吧.. 我会让这个问题再长一点，然后看看我能多快地构建一个原型解析器非此即彼。
再长一点
ANTLR looks to be an alternative path to the more common (OK I heard about them before) YACC/BISON approach, which it turns out also commonly use LEX/FLEX as a front end.
a Quick read of the FLEX man page kind of make me think It could be the framework for that regex type of idea..
Ok.. I'll let this stew a little longer, then see how quickly I can build a prototype parser in one or the other.
and a little bit longer