几款开源MIPS CPU

Question

一搜有一驼
Plasma - most MIPS I(TM) opcodes
The Plasma CPU core supports interrupts and all MIPS I(TM) user mode instructions except unaligned load and store operations.

UART with FIFO buffer (for ALTERA devices)
Features: - Universal Asynchronous Receiver/Transmitter (UART) - receive FIFO and transmit FIFO each for 31 characters - programmable length and parity (stop bit fixed to one stop bit) - programmable baud rate - interrupt control - “auto RTS” and “auto CTS” feature - auto resynchonisation after framing errors - should work on the following devices from ALTERA®: Stratix, Cyclone, APEX, Excalibur, Mecury, ACEX, FLEX, MAX - tested on ALTERA-Excalibur EPXA1 with 16 MHz system clock together with the mips1-PLASMA processor (available at www.opencore.org). This core is not suitable for you - if you don't have a device form ALTERA® - if you need a UART transmitting 1.5 or 2 stop bits

K System
A new asynchronous processor, based on the MIPS 64-bit (R12000A / R14000A), which will be the foundation of the new K System asynchronous multiprocessing hypercomputer.

miniMIPS
The miniMIPS is a 5 stage pipeline based on the MIPS I instruction set which is a 32 bits RISC architecture. Nearly all the instructions are supported with some custom feaures added. The core has been prototyped on an FPGA during an internship. This project was developped during an student project from the ENSERG university in Grenoble, France.

pAVR
pAVR (pipelined AVR) is an 8 bit RISC controller, compatible with Atmel's AVR core, but about 3x faster in terms of both clock frequency and MIPS. It achieves this performance by using a deep pipeline (with 6 stages).

YACC-Yet Another CPU CPU
YACC (Yet Another CPU CPU) is MIPS I (TM) subset cpu written in Verilog-2001 HDL. YACC has 5 pipeline and shows 110DMIPS in stratix2 with synthesized allowable clock of 165MHz. It is independent design of plasma, although YACC uses gcc-elf-mips tools provided by Steve Rhords, author of plasma (Most mips written in VHDL). The core was developed by using Veritak Simulator, with post layout gate simulation, and tested by actual FPGAs, using Xilinx spartan3 starter kit and Cyclone by Altera,running 800 digits of pi calculation ,(255,223) Reed Solomon Error Correction ,and Interactive calculator written by C language.

UltraBIPS
UltraBIPS is a superscalar cpu design, which has some feathers below: MIPS32 Processor Core Family ISA level Compatible MIPS32 PRA Implement Wishbone Compatible Superscalar Architecture using Tomasulo's algorithm and extended to handle speculation Array Multiplier MMU with TLB ( ITLB + DTLB + JTLB ) compatible to MIPS virtual address map MIPS CP0 Implement 3 Models: User model, Kernel model, Debug model Cache Implement (I$ + D$) SOC VGA Interface Block SOC PS/2 Keyboard Interface Block Both System C v2.01 Description and VHDL Description

mips r2000 subset
I will create a MIPS R2000 core in VHDL for Spartan-3 FPGAs using the free XST synthesizer provided by Xilinx. This core is part of a project for a course named "Advanced Digital Design", that I attended during my postgraduate studies in Microelectronics. The core will be ready at the end of September 2005 and will support the following instructions: LW, SW, ADDI, ADDIU, ANDI, ORI, XORI, ADD, ADDU, SUB, SUBU, ADN, OR, XOR, NOR, MULT, MULTU, SLL, SRL, SRA, SLLV, SRLV, SRAV, SLTI, SLTIU, SLT, SLTU, BEQ, BNE, JR. The initial version of the core will have 512 x 32 bytes data memory and 512 x 32 bytes of instruction memory.

UCore
UCore is a RISC microprocessor compatible of the MIPS32R2 Instruction Set. It can run all the MIPS32R2 instructions except the branch likely instructions. For these instructions are not recommended in the specification. The processor has 6 pipeline stages: Instruction Fetch (IF), Instruction Decode (ID), Register Fetch (RF), Execution (EX), Memory Access (MEM) and Write Back (WB). The processor uses synchronous ram as its Register file, data RAM and instruction RAM, which makes it be easily implemented in both FPGA and ASIC, especially in FPGA. The processor`s instruction set and privilege resource are designed strictly to the gMIPS32 Architecture for Programmersh (Volume I-IIICRevision 2.50) specification from MIPS Technologies Inc. The processor has been implemented in FPGA and synthesized by Design Compiler using UMC .18 ASIC libraries. When MMU and Caches are disabled, it can run at a speed 150MHz and occupies 3000 LUTs in Xilinx XC2VP30 (using Synplify 8.1 Pro and ISE 7.1i) FPGA; when implemented in Altera EP2C35 (using Quartus 6.0) FPGA, it can run at a speed of 120MHz and occupies 3300 LEs. When using a MMU with 64 entries of fully associated TLBs, an 8KB data cache and an 8KB instruction cache, it occupies 13300 LUTs and can run at 46 MHz in XCV4LX160 FPGA. According to the synthesis results of Design Compiler, the speed of the processor is 480 MHz and its power consumption is 197.6mW in Virtual Siliconfs UMC .18 ASIC libraries, occupying 0.466 square millimeter silicon or 23,000 equivalents gates. Many programs have been ported to the processor and tested on FPGA. They are uC/OS II, U-Boot, UIP/LWIP, Dhrystone, WEB&NAT server and so on. There are also some small test programs. The first one is an assembly program modified from the Plasma core written by Steve Rhoads, it tests all the instruction of UCore processor. The second and third ones are a 1000bits PI calculation program and a program sorting 10 short integers, which are written in C and compiled using GCC MIPS cross compiler. Programs used to test the SDRAM, Flash, SRAM, VGA modules and a program used to download Motorola S-record format binary to the chip from UART are developed and tested, too. You can get detailed information from the Makefile locating in the tool dictionary. I have built a system using the processor core. It contains the UCore, a 32k data/instruction on-chip SRAM, a timer, a UART, a SRAM controller, a SDRAM controller, a Nor Flash Controller, a VGA controller and a MAC controller and packet buffer for it. The system has been tested on Alterafs DE2 board and a Xilinx XC2VP30 FPGA board at 50MHz. All the programs mentioned in the previous section have been successfully run in FPGA. I have run the Dhrystone benchmark version 2.1 in the system, and it's score is 141DMIPS when run at 100 MHz. I have used GCC 3.2.3 and GCC 4.0.0 cross tool chains to generate the codes, then I translated them to format I need using a Perl script wrote by myself. The scripts used to build the GNU tool chain is lying in test/utils dictionary, named build-gcc.sh. You can download the GNU tool chain source and use the script to build a cross tool chain of yourself. I have verified the processor carefully. If anyone finds there are bugs in it, please let me know. Ifll fix it as quickly as possible. My email is whitewill@163.com. The code can be downloaded from the download section. The URL is http://www.opencores.org/pdownloads.cgi/list/ucore. Itfs an old version of the system. The latest version will be uploaded to CVS repository latter.

SardMIPS
It's a synthesizable parametric IP core of 32 bit RISC processor supporting full MIPS R2000 ISA, by using SystemC HDL. An optional CP0 coprocessor implementing full exception handling was also modelled. Also 64 bit pipeline multiplier supporting is optional, and pipeline depth is configurable.

Cowgirl
This is a processor core based on an instruction set I came up with. It's mostly a copy of a MIPS-type RISC architecture. Right now it's in the fairly early stages, but it is working for ~80% of the instructions.

mips789
This is a ip cpu core with five pipeline stages which supports amost MIPSI instructions.I tested is by using a lot of C program in the CYCLONE device EP1C6Q240 with 50MHZ and it worked so well .By calculation ,it's CPI is about 1.1 when run common program.I wish it would be used in real productions so I punish it in opencores.org

ocmips
Ocmips is a processor which is compatible with MIPS32 instruction set, it . It uses havard architecture which has different instruction and data memory. It is pipelined with six stages, that is IF : instruction fetch ID : instruction decode OP : alu operand EX : excute instruction MEM : memroy operation WB : write back Currently, it has been tested with a lot of C programs which compiled by GCC for mips compiler, and no bugs were found.

LWMIPS
Low Weight MIPS core for embedded system use. I tested it by running a lot of C programs.

r2000 Soc
- MIPS2000 32 bit RISC Pipeline 5 Stages - Multiplicator/Divisor 32bits - Exception/interrupt Risc Pipeline - Instruction & Data Cache Memory System - WishBone Compatible - MMU

mips single cycle microprocessor
implementation of mips single cycle microprocessor in verilog hdl.Code is fully synthesiziable.

[ 本帖最后由 bukaihua 于 2009-4-6 09:44 编辑 ]

Answer 1

没配网站啊

Answer 2

mips好像比较简单，很多嵌入式cpu都是直接抄mips指令集

Answer 3

原帖由 epegasus 于 2009-4-6 16:59 发表
没配网站啊

有链接，你点一下就看到了，都是opencores.org上的项目；
其中Ucore是中科院计算所的人写的。

Answer 4

实在是太强大了。 我现在就是需要MIPS CPU的开发方法。

Answer 5

和CPU的生产线介绍，CPU生产工具和工艺介绍。

Answer 6

  呵呵。

Answer 7

学习了.