ISE 综合通过， 但在布局布线时报错

Question

1. ISE调用IP核ram。语法、综合均通过了，端口例化也正确，但是在布局布线时显示

File "ipcore_dir/ram_test.ngc" cannot be merged into block "Instant_ram_test_1" (TYPE="ram_test") because one or more pins on the block, including pin "wea", were not found in the file. Please make sure that all pins on the instantiated component match pins in the lower-level design block (irrespective of case). If there are bussed pins on this block, make sure that the upper-level and lower-level netlists use the same bus-naming convention.(文件“ipcore_dir / ram_test.ngc”无法合并到块“Instant_ram_test_1”（TYPE =“ram_test”）中，因为块中的一个或多个引脚（包括引脚“wea”）未在文件中找到。 请确保实例化组件上的所有引脚都与较低级别设计模块中的引脚匹配（无论情况如何）。 如果此块上有总线引脚，请确保上层和下层网表使用相同的总线命名约定。)

1. 代码如下：

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;


entity test_bram_memory is
    port (
        data_in    :     in  STD_LOGIC_VECTOR (63  downto 0);
        wr_en        :     in  STD_LOGIC;    
        clk         :  in  STD_LOGIC;
        addr        :     in  STD_LOGIC_VECTOR (16 downto 0);
        rst_n        :     in  STD_LOGIC;
        ena        :    in  STD_LOGIC;
        data_out    :     out STD_LOGIC_VECTOR (63 downto 0);
        data_en     :     out STD_LOGIC
    );
end test_bram_memory;

architecture Behavioral of test_bram_memory is

    COMPONENT ram_test IS 
    port(
        clka        :  in  STD_LOGIC;   
        wea        :    in  STD_LOGIC;
        dina        :     in  STD_LOGIC_VECTOR (63  downto  0);
        addra        :     in  STD_LOGIC_VECTOR (16 downto  0);
        ena        :    in  STD_LOGIC;
        rsta        :  in  STD_LOGIC;
        douta        :  out STD_LOGIC_VECTOR (63  downto  0)
    );
    END COMPONENT;
    
begin
    
    process (clk, rst_n)
    begin
        if (rst_n = '0') then 
            data_en <= '0';
        elsif (falling_edge(clk)) then
            data_en <= wr_en;
        end if;
    end process;

Instant_ram_test_1    : ram_test  port map (
    clka     =>     clk,
    wea     =>     wr_en,
    dina     =>     data_in,
    addra =>     addr,
    ena    =>     ena,
    rsta  =>      rst_n,
    douta =>     data_out
);

END Behavioral;

求大佬帮助，谢谢了