Question

local_parameter_declaration ::=           // 引用自附录A.2.1.1
    localparam data_type_or_implicit list_of_param_assignments;

parameter_declaration ::=
    parameter data_type_or_implicit list_of_param_assignments
  | parameter type list_of_type_assignments

specparam_declaration ::=
    specparam [packed_dimension] list_of_specparam_assignments;

data_type_or_implicit ::=                // 引用自附录A.2.2.1
    data_type
  | [signing] {packed_dimension}

list_of_param_assignments ::= param_assignment {, param_assignment} // 引用自附录A.2.3

list_of_specparam_assignments ::= specparam_assignment {, specparam_assignment}

list_of_type_assignments ::= type_assignment {, type_assignment}

param_assignment ::=                    // 引用自附录A.2.4
    parameter_identifier {unpacked_dimension} = constant_param_expression

specparam_assignment ::=
    specparam_identifier = constant_mintypmax_expression
  | pulse_control_specparam

type_assignment ::= type_identifier = data_type

parameter_port_list ::=                // 引用自附录A.1.4
    #(list_of_param_assignments {, parameter_port_declaration})
  | #(parameter_port_declaration {, parameter_port_declaration})

parameter_port_declaration ::=
    parameter_declaration
  | data_type list_of_param_assignments
  | type list_of_type_assignments

语法 21-1 — 参数声明语法（摘录自附录A）

A module, interface, program or class can have parameters, which are set during elaboration and are constant during simulation. They are defined with data types and default values. With SystemVerilog, if no data type is supplied, parameters default to type logic of arbitrary size for Verilog-2001 compatibility and interoperability. SystemVerilog adds the ability for a parameter to also specify a data type, allowing modules or instances to have data whose type is set for each instance.

module ma #(parameter p1 = 1, parameter type p2 = shortint)
          (input logic [p1:0] i, output logic [p1:0] o);
    p2 j = 0; // type of j is set by a parameter, (shortint unless redefined)

    always @(i) begin
        o = i;
        j++;
    end
endmodule

module mb;
    logic [3:0] i,o;
    ma #(.p1(3), .p2(int)) u1(i,o); //redefines p2 to a type of int
endmodule

SystemVerilog adds the ability for local parameters to be declared in a generate block. Local parameters can also be declared in a package or in a compilation unit scope. In these contexts, the parameter keyword can be used as a synonym for the localparam keyword.

$ can be assigned to parameters of integer types. A parameter to which $ is assigned shall only be used wherever $ can be specified as a literal constant.

For example, $ represents unbounded range specification, where the upper index can be any integer.

parameter r2 = $;

property inq1(r1,r2);
    @(posedge clk) a ##[r1:r2] b ##1 c |=> d;
endproperty

assert inq1(3);

To support whether a constant is $, a system function is provided to test whether a constant is a $. The syntax of the system function is

$isunbounded(const_expression);

$isunbounded returns true if const_expression is unbounded. Typically, $isunbounded would be used as a condition in the generate statement.

The example below illustrates the benefit of using $ in writing properties concisely where the range is parameterized. The checker in the example ensures that a bus driven by signal en remains 0, i.e, quiet for the specified minimum (min_quiet) and maximum (max_quiet) quiet time.

Note that function $isunbounded is used for checking the validity of the actual arguments.

interface quiet_time_checker #(parameter min_quiet = 0,
                               parameter max_quiet = 0)
                              (input logic clk, reset_n, [1:0]en);
    generate
        if ( max_quiet == 0) begin
            property quiet_time;
                @(posedge clk) reset_n |-> ($countones(en) == 1);
            endproperty
            a1: assert property (quiet_time);
        end
        else begin
            property quiet_time;
                @(posedge clk)
                    (reset_n && ($past(en) != 0) && en == 0)
                    |->(en == 0)[*min_quiet:max_quiet]
                ##1 ($countones(en) == 1);
            endproperty
            a1: assert property (quiet_time);
        end

        if ((min_quiet == 0) && ($isunbounded(max_quiet))
            $display(warning_msg);
    endgenerate
endinterface

quiet_time_checker #(0, 0) quiet_never (clk,1,enables);
quiet_time_checker #(2, 4) quiet_in_window (clk,1,enables);
quiet_time_checker #(0, $) quiet_any (clk,1,enables);

Another example below illustrates that by testing for $, a property can be configured according to the requirements. When parameter max_cks is unbounded, it is not required to test for expr to become false.

interface width_checker #(parameter min_cks = 1, parameter max_cks = 1)
                         (input logic clk, reset_n, expr);
    generate begin
        if ($isunbounded(max_cks)) begin
            property width;
                @(posedge clk)
                    (reset_n && $rose(expr)) |-> (expr [* min_cks]);
            endproperty

            a2: assert property (width);
        end
        else begin
            property assert_width_p;
                @(posedge clk)
                    (reset_n && $rose(expr)) |-> (expr[* min_cks:max_cks])
                    ##1 (!expr);
            endproperty

            a2: assert property (width);
        end
    endgenerate
endinterface

width_checker #(3, $) max_width_unspecified (clk,1,enables);
width_checker #(2, 4) width_specified (clk,1,enables);

SystemVerilog also adds the ability to omit the parameter keyword in a parameter port list.

class vector #(size = 1);
    logic [size-1:0] v;
endclass

typedef vector#(16) word;

interface simple_bus #(AWIDTH = 64, type T = word) (input bit clk) ;
endinterface

In a list of parameters, a parameter can depend on earlier parameters. In the following declaration, the default value of the second parameter depends on the value of the first parameter. The third parameter is a type, and the fourth parameter is a value of that type.

module mc #(int N = 5, M = N*16, type T = int, T x = 0)
           ( ... );
    ...
endmodule