Question

Coverage tools need to have automatic recognition of many of the common FSM coding idioms in Verilog/ SystemVerilog. This standard does not attempt to describe or require any specific automatic FSM recognition mechanisms. However, the standard does prescribe a means by which non-automatic FSM extraction occurs. The presence of any of these standard FSM description additions shall override the tool’s default extraction mechanism.

Identification of an FSM consists of identifying the following items:

1. the state register (or expression)
2. the next state register (this is optional)
3. the legal states.