Question

In Verilog, the `define macro text can include a backslash ( \ ) at the end of a line to show continuation on the next line.

In SystemVerilog, the macro text can also include `", `\`" and ``.

An `" overrides the usual lexical meaning of ", and indicates that the expansion should include an actual quotation mark. This allows string literals to be constructed from macro arguments.

A `\`" indicates that the expansion should include the escape sequence \", e.g.

`define msg(x,y) `"x: `\`"y`\`"`"

This expands:

$display(`msg(left side,right side));

to:

$display("left side: \"right side\"");

A `` delimits lexical tokens without introducing white space, allowing identifiers to be constructed from arguments, e.g.

`define foo(f) f``_suffix

This expands:

‘foo(bar)

to:

bar_suffix

The ‘include directive can be followed by a macro, instead of a literal string:

‘define home(filename) ‘"/home/foo/filename‘"
‘include ‘home(myfile)