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26.1 简介（一般信息）	Certain Verilog language features can be simulation inefficient, easily abused, and the source of design problems. These features are being considered for removal from the SystemVerilog language, if there is an alternate method for these features. The Verilog language features that have been identified in this standard as ones which can be removed from Verilog are defparam and procedural assign/deassign.
26.2 defparam语句	The SystemVerilog committee has determined, based on the solicitation of input from tool implementers and tools users, that the defparam method of specifying the value of a parameter can be a source of design errors, and can be an impediment to tool implementation. The defparam statement does not provide a capability that cannot be done by another method, which avoids these problems. Therefore, the committee has placed the defparam statement on a deprecation list. This means is that a future revision of the Verilog standard might not require support for this feature. This current standard still requires tools to support... more
26.3 过程赋值与解赋值语句	The SystemVerilog committee has determined, based on the solicitation of input from tool implementers and tools users, that the procedural assign and deassign statements can be a source of design errors, and can be an impediment to tool implementation. The procedural assign/deassign statements do not provide a capability that cannot be done by another method, which avoids these problems. Therefore, the committee has placed the procedural assign/deassign statements on a deprecation list. This means that a future revision of the Verilog standard might not require support for theses statements. This current standard still requires tools to support the procedural assign/deassign... more

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