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18.1 简介（一般信息）	Verilog的组织结构较为简单。除系统任务和系统函数外，所有的数据、函数和任务都位于模块当中（系统任务和系统函数是全局的，并且可以在PLI中定义）。Verilog模块可以包含其它模块的实例。任何未被实例化的模块都位于顶层。这个规则不适用于库，因此库具有不同的状态和不同的过程来进行分析。一个层次名可以在实例层次的任何地方指定任何命名的对象。模块层次通常很随意，需要耗费很多精力来维护端口列表。 在Verilog中，只有线网、reg、integer和时间数据类型才可以通过模块端口传递。 为了表示设计层次，SystemVerilog加入了许多增强： 包含诸如数据、类型、类、任务和函数声明的包 支持分离的编译 仅在编译单元内可见的编译单元范围 使用嵌套的模块声明来帮助表示自包含的模块和库 在端口声明中可以使用较宽松的规则 使用“.name”来简化命名端口的连接 使用“.”的隐式端口连接 与模块绑定的时间单位和时间精度说明 使用接口的概念来封装模块间的连接（在第十九章中提供） SystemVerilog的一个重要增强就是加入了通过模块端口传递任何数据类型的能力，包括线网、以及包括实数、数组和结构体在内的所有变量类型。
18.2 包	SystemVerilog包提供了额外的机制在多个SystemVerilog模块、接口和程序间共享参数、数据、类型、任务、函数、序列以及特性的声明。包是显式命名的作用域，它出现在源文本的最外层（与顶层模块和原语处于同一层次）。类型、变量、任务、函数以及特性都可以在一个包中声明。这些声明可以在模块、宏模块、接口、程序和其它包中通过导入或完整解析的名字来引用。
18.3 编译单元的支持	通过使用编译单元，SystemVerilog支持分离的编译。SystemVerilog提供了下列的术语和定义： 编译单元：a collection of one or more SystemVerilog source files compiled together 编译单元作用域：a scope that is local to the compilation unit. It contains all declarations that lie outside of any other scope $unit：用来显式地访问编译单元作用域中的标识符的名字 The exact mechanism for defining which files constitute a compilation unit is tool specific. Tools shall provide a mechanism to specify the files that make up a compilation unit. Two extreme cases are: All files make a single compilation unit (in which case the declarations in the compilation-unit scope are accessible anywhere within the design) Each file is a separate compilation unit (in which case the... more
18.4 顶层实例	The name $root is added to unambiguously refer to a top level instance, or to an instance path starting from the root of the instantiation tree. $root is the root of the instantiation tree. For example:
18.5 模块声明
18.6 嵌套的模块	A module can be declared within another module. The outer name space is visible to the inner module, so that any name declared there can be used, unless hidden by a local name, provided the module is declared and instantiated in the same scope. One purpose of nesting modules is to show the logical partitioning of a module without using ports. Names that are global are in the outermost scope, and names that are only used locally can be limited to local modules.
18.7 外部模块	To support separate compilation, extern declarations of a module can be used to declare the ports on a module without defining the module itself. An extern module declaration consists of the keyword extern followed by the module name and the list of ports for the module. Both list of ports syntax (possibly with parameters), and original Verilog style port declarations can be used. Note that the potential existence of defparams precludes the checking of the port connection information prior to elaboration time even for list of ports style declarations. The following example demonstrates the usage of extern module declarations.
18.8 端口声明
18.9 端口表达式列表	Verilog 1364-2001 created a list_of_port_declarations alternate style which minimized the duplication of data used to specify the ports of a module. SystemVerilog adds an explicitly named port declaration to that style, allowing elements of arrays and structures, concatenations of elements, or aggregate expressions of elements declared in a module, interface or program to be specified on the port list. Like explicitly named ports in a module port declaration, port identifiers exist in their own namespace for each port list. When port item is just a simple port identifier, that identifier is used as both a reference to an interface item... more
18.10 时间单位与精度	SystemVerilog has a time unit and precision declaration which has the equivalent functionality of the ‘timescale compiler directives in Verilog-2001. Use of these declarations removes the file order dependencies problems with compiler directives. The time unit and precision can be declared by the timeunit and timeprecision keywords, respectively, and set to a time literal which must be a power of 10 units. For example:
18.11 模块实例
18.12 端口连接规则	通过允许所有变量数据类型都能够通过端口传递，SystemVerilog扩展了Verilog的端口连接能力。通过允许端口连接的两侧具有相同的兼容类型，并且通过允许对变量的连续赋值，SystemVerilog做到了这一点。SystemVerilog还产生了一个新的端口限定符类型，ref，它允许共享的变量通过传递一个层次化的引用来跨越一个端口。
18.13 命名空间	SystemVerilog has eight name spaces for identifiers, two are global (definitions name space and package name space), two are global to the compilation unit (compilation unit name space and text macro name space) and four are local. The eight name spaces are described as follows: The definitions name space unifies all the non-nested module, macromodule, primitive, program, and interface identifiers defined outside of all other declarations. Once a name is used to define a module, macromodule, primitive, program, or interface within one compilation unit the name shall not be used again (in any compilation unit) to declare another non-nested module,... more
18.14 层次化的名字	Hierarchical names are also called nested identifiers. They consist of instance names separated by periods, where an instance name can be an array element. The instance name $root refers to the top of the instantiated design and is used to unambiguously gain access to the top of the design.

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