Question

blocking_assignment ::=    // 引用自附录A.6.2
    variable_lvalue = delay_or_event_control expression
  | hierarchical_dynamic_array_variable_identifier = dynamic_array_new
  | [implicit_class_handle.|class_scope|package_scope]hierarchical_variable_identifier
        select = class_new
  | operator_assignment

operator_assignment ::= variable_lvalue assignment_operator expression

assignment_operator ::=
    = | += | -= | *= | /= | %= | &= | |= | ^= | <<= | >>= | <<<= | >>>=

nonblocking_assignment ::= variable_lvalue <= [delay_or_event_control] expression

语法 8-2—阻塞与无阻塞赋值语法（摘录自附录A）

下列的赋值语句在Verilog-2001和SystemVerilog中都是合法的：

#1 r = a;
r = #1 a;
r <= #1 a;
r <= a;
@c r = a;
r = @c a;
r <= @c a;

在赋值语句中，SystemVerilog还允许指定一个时间单位，例如：

#1ns r = a;
r = #1ns a;
r <= #1ns a;

为自动变量进行无阻塞赋值是非法的。

赋值语句左侧的尺寸形成了右侧表达式的关联文。如果左侧尺寸小于右侧表达式尺寸，信息可能会丢失，并且可以给出警告信息。