Question

The SystemVerilog committee has determined, based on the solicitation of input from tool implementers and tools users, that the procedural assign and deassign statements can be a source of design errors, and can be an impediment to tool implementation. The procedural assign/deassign statements do not provide a capability that cannot be done by another method, which avoids these problems. Therefore, the committee has placed the procedural assign/deassign statements on a deprecation list. This means that a future revision of the Verilog standard might not require support for theses statements. This current standard still requires tools to support the procedural assign/deassign statements. However, users are strongly encouraged to migrate their code to use one of the alternate methods of procedural or continuous assignments.

Verilog has two forms of the assign statement:

• Continuous assignments, placed outside of any procedures
• Procedural continuous assignments, placed within a procedure

Continuous assignment statements are a separate process that are active throughout simulation. The continuous assignment statement accurately represents combinational logic at an RTL level of modeling, and is frequently used.

Procedural continuous assignment statements become active when the assign statement is executed in the procedure. The process can be de-activated using a deassign statement. The procedural assign/deassign statements are seldom needed to model hardware behavior. In the unusual circumstances where the behavior of procedural continuous assignments are required, the same behavior can be modeled using the procedural force and release statements.

The fact that the assign statement to be used both outside and inside a procedure can cause confusion and errors in Verilog models. The practice of using the assign and deassign statements inside of procedural blocks is highly discouraged.