Question

SystemVerilog extends the Verilog Procedural Interface (VPI) object diagrams to support SystemVerilog constructs. The VPI object diagrams document the properties of objects and the relationships of objects. How these diagrams illustrate this information is explained in Section 26 of the IEEE Std. 1364-2001 Verilog standard. The SystemVerilog extensions to the VPI diagrams are in the form of changes to or additions to the diagrams contained in 1364-2001 Verilog standard.

The following table summarizes the changes and additions made to the Verilog VPI object diagrams:

Table 31-4: Verilog VPI object diagram changes and additions

Diagram	Notes
Instances	New
Interface	New
Program	New
Module	Replaces IEEE 1364.2001 section 26.6.1
Modport	New
Interface tf decl	New
Ports	Replaces IEEE 1364.2001, section 26.6.5
Ref Obj	New
Variable	Replaces IEEE 1364.2001 section 26.6.8
Var select	New
Typespec	New
Variable Drivers and Loads	New
Instance Arrays	Replaces IEEE 1364.2001 section 26.6.2
Scope	Replaces IEEE 1364.2001 section 26.6.3
IO Declaration	Replaces IEEE 1364.2001 section 26.6.4
Class Object Definition	New
Constraint	New
Dist Item	New
Constraint Expression	New
Class Variables	New
Structure/Union	New
Named Events	New
Named Event Array	New
Task, Function Declaration	Replaces IEEE 1364.2001 section 26.6.18
Alias Statement	New
Frames	Replaces IEEE 1364.2001 section 26.6.20
Threads	New
Concurrent Assertions	New
Disable Condition	New
Clocking Event	New
Property Declaration	New
Property Specification	New
Property Expression	New
Multiclock Sequence Expression	New
Sequence Declaration	New
Sequence Expression	New
Instances	New
Atomic Statement	New
if, if-else	Replaces IEEE 1364-2001 section 26.6.35
case	Replaces IEEE 1364-2001 section 26.6.36
return	New
do while	New
waits	Replaces wait in IEEE 1364-2001 section 26.6.32
disables	Replaces IEEE 1364-2001 section 26.6 38
expect	New
foreach	New