Question

loop_statement ::=                // 引用自附录A.6.8
    forever statement_or_null
  | repeat (expression) statement_or_null
  | while (expression) statement_or_null
  | for (for_initialization; expression; for_step)
        statement_or_null
  | do statement_or_null while (expression);
  | foreach (array_identifier[loop_variables]) statement

for_initialization ::=
    list_of_variable_assignments
  | data_type list_of_variable_assignments {,data_type list_of_variable_assignments}

for_step ::= for_step_assignment {,for_step_assignment}

for_step_assignment ::=
    operator_assignment
  | inc_or_dec_expression

loop_variables ::= [index_variable_identifier]{,[index_variable_identifier]}

语法 8-5—循环语句语法（摘录自附录A）

Verilog提供了for、while、repeat以及forever循环。SystemVerilog增强了Verilog的for循环，并加入了一个do...while循环和一个foreach循环。