Question

Verilog provides the ‘define text substitution macro compiler directive. A macro can contain arguments, whose values can be set for each instance of the macro. For example:

‘define NAND(dval) nand #(dval)
‘NAND(3) i1 (y, a, b); //‘NAND(3) macro substitutes with: nand #(3)
‘NAND(3:4:5) i2 (o, c, d); //‘NAND(3:4:5) macro substitutes with: nand
#(3:4:5)

SystemVerilog enhances the capabilities of the ‘define compiler directive to support the construction of string literals and identifiers.

Verilog provides the `include file inclusion compiler directive. SystemVerilog enhances the capabilities to support standard include specification, and enhances the `include directive to accept a file name constructed with a macro.