- 第一章 SystemVerilog导论
- 第二章 文本值
- 第三章 数据类型
- 第四章 数组
- 第五章 数据声明
- 第六章 属性
- 第七章 操作符与表达式
- 第八章 过程语句和控制流
- 第九章 进程
- 第十章 任务与函数
- 第十一章 类
- 第十二章 随机约束
- 第十三章 进程间的同步与通信
- 第十四章 调度语义
- 第十五章 时钟控制块
- 第十六章 程序块
- 第十七章 断言
- 第十八章 层次
- 第十九章 接口
- 第二十章 覆盖
- 第二十一章 参数
- 第二十二章 配置库
- 第二十三章 系统任务与系统函数
- 23.1 简介(一般信息)
- 23.2 确立时的typeof函数
- 23.3 typename函数
- 23.4 表达式尺寸系统函数
- 23.5 范围系统函数
- 23.6 Shortreal转换
- 23.7 数组查询系统函数
- 23.8 断言严重性系统任务
- 23.9 断言控制系统任务
- 23.10 断言系统函数
- 23.11 随机数系统函数
- 23.12 程序控制
- 23.13 覆盖系统函数
- 23.14 对Verilog-2001系统任务的增强
- 23.15 $readmemb与$readmemh
- 23.16 $writememb and $writememh
- 23.17 File format considerations for multi-dimensional unpacked arrays
- 23.18 System task arguments for multi-dimensional unpacked arrays
- 第二十四章 VCD数据
- 第二十五章 编译器指令
- 第二十六章 考虑从SystemVerilog中删除的功能
- 第二十七章 直接编程接口(DPI)
- 27.1 概述
- 27.2 Two layers of the DPI
- 27.3 Global name space of imported and exported functions
- 27.4 导入的任务和函数
- 27.5 Calling imported functions
- 27.6 Exported functions
- 27.7 Exported tasks
- 27.8 Disabling DPI tasks and functions
- 第二十八章 SystemVerilog断言API
- 第二十九章 SystemVerilog覆盖API
- 29.1 需求
- 29.2 SystemVerilog real-time coverage access
- 29.3 FSM recognition
- 29.3.1 Specifying the signal that holds the current state
- 29.3.2 Specifying the part-select that holds the current state
- 29.3.3 Specifying the concatenation that holds the current state
- 29.3.4 Specifying the signal that holds the next state
- 29.3.5 Specifying the current and next state signals in the same declaration
- 29.3.6 Specifying the possible states of the FSM
- 29.3.7 Pragmas in one-line comments
- 29.3.8 Example
- 29.4 VPI coverage extensions
- 第三十章 SystemVerilog数据读API
- 30.1 简介(一般信息)
- 30.2 需求
- 30.3 Extensions to VPI enumerations
- 30.4 VPI object type additions
- 30.5 Object model diagrams
- 30.6 Usage extensions to VPI routines
- 30.7 VPI routines added in SystemVerilog
- 30.8 Reading data
- 30.9 Optionally unloading the data
- 30.10 Reading data from multiple databases and/or different read library providers
- 30.11 VPI routines extended in SystemVerilog
- 30.12 VPI routines added in SystemVerilog
- 30.12.1 VPI reader routines
- 第三十一章 SystemVerilog VPI Object Model
- 31.1 简介(一般信息)
- 31.2 Instance
- 31.3 Interface
- 31.4 Program
- 31.5 Module (supersedes IEEE 1364-2001 26.6.1)
- 31.6 Modport
- 31.7 Interface tf decl
- 31.8 Ports (supersedes IEEE 1364-2001 26.6.5)
- 31.9 Ref Obj
- 31.9.1 Examples
- 31.10 Variables (supersedes IEEE 1364-2001 section 26.6.8)
- 31.11 Var Select (supersedes IEEE 1364-2001 26.6.8)
- 31.12 Typespec
- 31.13 Variable Drivers and Loads (supersedes IEEE 1364-2001 26.6.23)
- 31.14 Instance Arrays (supersedes IEEE 1364-2001 26.6.2)
- 31.15 Scope (supersedes IEEE 1364-2001 26.6.3)
- 31.16 IO Declaration (supersedes IEEE 1364-2001 26.6.4)
- 31.17 Clocking Block
- 31.18 Class Object Definition
- 31.19 Constraint, constraint ordering, distribution,
- 31.20 Constraint expression
- 31.21 Class Variables
- 31.22 Structure/Union
- 31.23 Named Events (supersedes IEEE 1364-2001 26.6.11)
- 31.24 Task, Function Declaration (supersedes IEEE 1364-2001 26.6.18)
- 31.25 Alias Statement
- 31.25.1 Examples
- 31.26 Frames (supersedes IEEE 1364-2001 26.6.20)
- 31.27 Threads
- 31.28 tf call (supersedes IEEE 1364-2001 26.6.19)
- 31.29 Module path, path term (supersedes IEEE 1364-2001 26.6.15)
- 31.30 Concurrent assertions
- 31.31 Property Decl
- 31.32 Property Specification
- 31.33 Multiclock Sequence Expression
- 31.34 Sequence Declaration
- 31.35 Sequence Expression
- 31.36 Attribute (supersedes IEEE 1364-2001 26.6.42)
- 31.37 Atomic Statement (supersedes IEEE 1364-2001 26.6.27)
- 31.38 If, if else, return, case, do while (supersedes IEEE 1364-2001 26.6.35, 26.6.36)
- 31.39 waits, disables, expect, foreach (supersedes IEEE 1364 26.6.38)
- 31.40 Simple expressions (supersedes IEEE 1364-2001 26.6.25)
- 31.41 Expressions (supersedes IEEE 1364-2001 26.6.26)
- 31.42 Event control (supersedes IEEE 1364-2001 26.6.30)
- 31.43 Event stmt (supersedes IEEE 1364-2001 26.6.27)
- 31.44 Process (supersedes IEEE 1364-2001 26.6.27)
- 31.45 Assignment (supersedes IEEE 1364-2001 26.6.28)
- 附录A 形式语法
- A.1 源文本
- A.2 声明
- A.3 Primitive instances
- A.4 Module, interface and generated instantiation
- A.5 UDP declaration and instantiation
- A.6 Behavioral statements
- A.6.1 Continuous assignment and net alias statements
- A.6.2 Procedural blocks and assignments
- A.6.3 Parallel and sequential blocks
- A.6.4 Statements
- A.6.5 Timing control statements
- A.6.6 Conditional statements
- A.6.7 Case statements
- A.6.8 Looping statements
- A.6.9 Subroutine call statements
- A.6.10 Assertion statements
- A.6.11 Clocking block
- A.6.12 Randsequence
- A.7 Specify section
- A.8 Expressions
- A.9 General
- A.10 Footnotes (normative)
- 附录B 关键字
- 附录C 标准包
- 附录D 链表
- 附录E DPI C-layer
- E.1 概述
- E.2 Naming conventions
- E.3 Portability
- E.4 Include files
- E.5 Semantic constraints
- E.6 Data types
- E.7 Argument passing modes
- E.8 Context tasks and functions
- E.9 Include files
- E.10 Arrays
- E.11 Open arrays
- E.11.1 Actual ranges
- E.11.2 Array querying functions
- E.11.3 Access functions
- E.11.4 Access to the actual representation
- E.11.5 Access to elements via canonical representation
- E.11.6 Access to scalar elements (bit and logic)
- E.11.7 Access to array elements of other types
- E.11.8 Example 4— two-dimensional open array
- E.11.9 Example 5 — open array
- E.11.10 Example 6 — access to packed arrays
- E.11.11 Example 7 — binary compatible calls of exported functions
- 附录F 包含文件
- 附录G 包含外部语言代码
- 附录H 并发断言的形式语义
- 附录I svvpiuser.h
- 附录J 术语表
- 附录K 参考书目
- 其他
17.14.1 在多时钟控制特性中的时钟解析
Throughout this subsection, s, s1, s2 denote sequences without clocking events; p, p1, p2 denote properties without clocking events; m, m1, m2 denote multiply-clocked sequences, q, q1, q2 denote multiply-clocked properties; and c, c1, c2 denote non-identical clocking event expressions.
Due to clock flow, juxtaposition of two clocks nullifies the first. This and the nesting of clocking events within other property building operators mean that there are subtleties in the general interpretation of the restrictions about where the clock can change in multiply-clocked properties. For example,
@(c) s |-> @(c) (p and @(c1) p1)
appears legal because the antecedent is clocked by c and the consequent begins syntactically with the clocking event @(c). However, the consequent sequence is equivalent to
(@(c) p) and (@(c1) p1)
and |-> cannot synchronize between clock c from the antecedent and clock c1 from the second conjunct of the consequent. Similarly,
@(c) s |-> @(c1) (@(c) p)
appears illegal due to the apparent clock change from c to c1 across |->. However, it is legal, although arguably misleading in style, because the consequent property is equivalent to @(c) p.
This subsection gives a more precise treatment of the restrictions on multiply-clocked use of |-> and if/if...else than the intuitive discussion in Section 17.12. The present treatment depends on the notion of the set of semantic leading clocks for a multiply-clocked sequence or property.
Some sequences and properties have no explicit leading clock event. Their initial clocking event is inherited from an outer clocking event according to the flow of clocking event scope. In this case, the semantic leading clock is said to be inherited. For example, in the property
@(c) s |=> p and @(c1) p1
the semantic leading clock of the subproperty p is inherited since the initial clock of p is the clock that flows
across |=>.
A multiply-clocked sequence has a unique semantic leading clock, defined inductively as follows.
- The semantic leading clock of s is inherited.
- The semantic leading clock of @(c) s is c.
- If inherited is the semantic leading clock of m, then the semantic leading clock of @(c) m is c. Otherwise, the semantic leading clock of @(c) m is equal to the semantic leading clock of m.
- The semantic leading clock of (m) is equal to the semantic leading clock of m.
- The semantic leading clock of m1 ## m2 is equal to the semantic leading clock of m1.
- The set of semantic leading clocks of m is {c}, where c is the unique semantic leading clock of m.
- The set of semantic leading clocks of p is {inherited}.
- If inherited is an element of the set of semantic leading clocks of q, then the set of semantic leading clocks of @(c) q is obtained from the set of semantic leading clocks of q by replacing inherited by c. Otherwise, the set of semantic leading clocks of @(c) q is equal to the set of semantic leading clocks of q.
- The set of semantic leading clocks of (q) is equal to the set of semantic leading clocks of q.
- The set of semantic leading clocks of not q is equal to the set of semantic leading clocks of q.
- The set of semantic leading clocks of q1 and q2 is the union of the set of semantic leading clocks of q1 with
- the set of semantic leading clocks of q2.
- The set of semantic leading clocks of q1 or q2 is the union of the set of semantic leading clocks of q1 with the set of semantic leading clocks of q2.
- The set of semantic leading clocks of m |-> p is equal to the set of semantic leading clocks of m.
- The set of semantic leading clocks of m |=> p is equal to the set of semantic leading clocks of m.
- The set of semantic leading clocks of if (b) q is {inherited}.
- The set of semantic leading clocks of if (b) q1 else q2 is {inherited}.
- The set of semantic leading clocks of a property instance is equal to the set of semantic leading clocks of the multiply-clocked property obtained from the body of its declaration by substituting in actual arguments.
@(c1) s1 ## @(c2) s2
has c1 as its unique semantic leading clock, while the multiply-clocked property
not (p1 and (@(c2) p2)
has {inherited, c2} as its set of semantic leading clocks.
In the presence of an incoming outer clock, the inherited semantic leading clock is always understood to refer to the incoming outer clock. On the other hand, if a property has only explicit semantic leading clocks, then the incoming outer clock has no effect on the clocking of the property since the explicit clock events replace the incoming outer clock. Therefore, the clocking of a property q in the presence of incoming outer clock c is equivalent to the clocking of the property @(c) q.
The rules for using multiply-clocked overlapping implication and if/if...else in the presence of an incoming outer clock can now be stated more precisely.
1) Multiply-clocked overlapping implication.
Let c be the incoming outer clock. Then the clocking of m |-> q is equivalent to the clocking of @(c) m |-> q
In the presence of the incoming outer clock, m has a well-defined ending clock, and there is a welldefined clock that flows across |->. The multiply-clocked overlapped implication m |-> q is legal for incoming clock c if and only if the following two conditions are met:
a) Every explicit semantic leading clock of q is identical to the ending clock of m.
b) If inherited is a semantic leading clock of q, then the ending clock of m is equal to the clock that flows across |->.
For example
@(c) s |-> p1 or @(c2) p2
is not legal because the ending clock of the antecedent is c, while the consequent has c2 as an explicit semantic leading clock.
Also,
@(c) s ## (@(c1) s1) |-> p
is not legal because the set of semantic leading clocks of p is {inherited}, the ending clock of the antecedent is c1, and the clock that flows across |-> and is inherited by p is c.
On the other hand,
@(c) s |-> p1 or @(c) p2
and
@(c) s ## @(c1) s1 |-> p1 or @(c1) p2
are both legal.
2) Multiply-clocked if/if...else
Let c be the incoming outer clock. Then the clocking of if (b) q1 [ else q2 ] is equivalent to the clocking
of
@(c) if (b) q1 [ else q2 ]
The boolean condition b is clocked by c, so the multiply-clocked if/if...else if (b) q1 [ else q2 ] is legal for incoming clock c if and only if the following condition is met:
- Every explicit semantic leading clock of q1 [ or q2 ] is identical to c.
@(c) if (b) p1 else @(c) p2
is legal, but
@(c) if (b) @(c) (p1 and @(c2) p2)
is not.
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