- 第一章 SystemVerilog导论
- 第二章 文本值
- 第三章 数据类型
- 第四章 数组
- 第五章 数据声明
- 第六章 属性
- 第七章 操作符与表达式
- 第八章 过程语句和控制流
- 第九章 进程
- 第十章 任务与函数
- 第十一章 类
- 第十二章 随机约束
- 第十三章 进程间的同步与通信
- 第十四章 调度语义
- 第十五章 时钟控制块
- 第十六章 程序块
- 第十七章 断言
- 第十八章 层次
- 第十九章 接口
- 第二十章 覆盖
- 第二十一章 参数
- 第二十二章 配置库
- 第二十三章 系统任务与系统函数
- 23.1 简介(一般信息)
- 23.2 确立时的typeof函数
- 23.3 typename函数
- 23.4 表达式尺寸系统函数
- 23.5 范围系统函数
- 23.6 Shortreal转换
- 23.7 数组查询系统函数
- 23.8 断言严重性系统任务
- 23.9 断言控制系统任务
- 23.10 断言系统函数
- 23.11 随机数系统函数
- 23.12 程序控制
- 23.13 覆盖系统函数
- 23.14 对Verilog-2001系统任务的增强
- 23.15 $readmemb与$readmemh
- 23.16 $writememb and $writememh
- 23.17 File format considerations for multi-dimensional unpacked arrays
- 23.18 System task arguments for multi-dimensional unpacked arrays
- 第二十四章 VCD数据
- 第二十五章 编译器指令
- 第二十六章 考虑从SystemVerilog中删除的功能
- 第二十七章 直接编程接口(DPI)
- 27.1 概述
- 27.2 Two layers of the DPI
- 27.3 Global name space of imported and exported functions
- 27.4 导入的任务和函数
- 27.5 Calling imported functions
- 27.6 Exported functions
- 27.7 Exported tasks
- 27.8 Disabling DPI tasks and functions
- 第二十八章 SystemVerilog断言API
- 第二十九章 SystemVerilog覆盖API
- 29.1 需求
- 29.2 SystemVerilog real-time coverage access
- 29.3 FSM recognition
- 29.3.1 Specifying the signal that holds the current state
- 29.3.2 Specifying the part-select that holds the current state
- 29.3.3 Specifying the concatenation that holds the current state
- 29.3.4 Specifying the signal that holds the next state
- 29.3.5 Specifying the current and next state signals in the same declaration
- 29.3.6 Specifying the possible states of the FSM
- 29.3.7 Pragmas in one-line comments
- 29.3.8 Example
- 29.4 VPI coverage extensions
- 第三十章 SystemVerilog数据读API
- 30.1 简介(一般信息)
- 30.2 需求
- 30.3 Extensions to VPI enumerations
- 30.4 VPI object type additions
- 30.5 Object model diagrams
- 30.6 Usage extensions to VPI routines
- 30.7 VPI routines added in SystemVerilog
- 30.8 Reading data
- 30.9 Optionally unloading the data
- 30.10 Reading data from multiple databases and/or different read library providers
- 30.11 VPI routines extended in SystemVerilog
- 30.12 VPI routines added in SystemVerilog
- 30.12.1 VPI reader routines
- 第三十一章 SystemVerilog VPI Object Model
- 31.1 简介(一般信息)
- 31.2 Instance
- 31.3 Interface
- 31.4 Program
- 31.5 Module (supersedes IEEE 1364-2001 26.6.1)
- 31.6 Modport
- 31.7 Interface tf decl
- 31.8 Ports (supersedes IEEE 1364-2001 26.6.5)
- 31.9 Ref Obj
- 31.9.1 Examples
- 31.10 Variables (supersedes IEEE 1364-2001 section 26.6.8)
- 31.11 Var Select (supersedes IEEE 1364-2001 26.6.8)
- 31.12 Typespec
- 31.13 Variable Drivers and Loads (supersedes IEEE 1364-2001 26.6.23)
- 31.14 Instance Arrays (supersedes IEEE 1364-2001 26.6.2)
- 31.15 Scope (supersedes IEEE 1364-2001 26.6.3)
- 31.16 IO Declaration (supersedes IEEE 1364-2001 26.6.4)
- 31.17 Clocking Block
- 31.18 Class Object Definition
- 31.19 Constraint, constraint ordering, distribution,
- 31.20 Constraint expression
- 31.21 Class Variables
- 31.22 Structure/Union
- 31.23 Named Events (supersedes IEEE 1364-2001 26.6.11)
- 31.24 Task, Function Declaration (supersedes IEEE 1364-2001 26.6.18)
- 31.25 Alias Statement
- 31.25.1 Examples
- 31.26 Frames (supersedes IEEE 1364-2001 26.6.20)
- 31.27 Threads
- 31.28 tf call (supersedes IEEE 1364-2001 26.6.19)
- 31.29 Module path, path term (supersedes IEEE 1364-2001 26.6.15)
- 31.30 Concurrent assertions
- 31.31 Property Decl
- 31.32 Property Specification
- 31.33 Multiclock Sequence Expression
- 31.34 Sequence Declaration
- 31.35 Sequence Expression
- 31.36 Attribute (supersedes IEEE 1364-2001 26.6.42)
- 31.37 Atomic Statement (supersedes IEEE 1364-2001 26.6.27)
- 31.38 If, if else, return, case, do while (supersedes IEEE 1364-2001 26.6.35, 26.6.36)
- 31.39 waits, disables, expect, foreach (supersedes IEEE 1364 26.6.38)
- 31.40 Simple expressions (supersedes IEEE 1364-2001 26.6.25)
- 31.41 Expressions (supersedes IEEE 1364-2001 26.6.26)
- 31.42 Event control (supersedes IEEE 1364-2001 26.6.30)
- 31.43 Event stmt (supersedes IEEE 1364-2001 26.6.27)
- 31.44 Process (supersedes IEEE 1364-2001 26.6.27)
- 31.45 Assignment (supersedes IEEE 1364-2001 26.6.28)
- 附录A 形式语法
- A.1 源文本
- A.2 声明
- A.3 Primitive instances
- A.4 Module, interface and generated instantiation
- A.5 UDP declaration and instantiation
- A.6 Behavioral statements
- A.6.1 Continuous assignment and net alias statements
- A.6.2 Procedural blocks and assignments
- A.6.3 Parallel and sequential blocks
- A.6.4 Statements
- A.6.5 Timing control statements
- A.6.6 Conditional statements
- A.6.7 Case statements
- A.6.8 Looping statements
- A.6.9 Subroutine call statements
- A.6.10 Assertion statements
- A.6.11 Clocking block
- A.6.12 Randsequence
- A.7 Specify section
- A.8 Expressions
- A.9 General
- A.10 Footnotes (normative)
- 附录B 关键字
- 附录C 标准包
- 附录D 链表
- 附录E DPI C-layer
- E.1 概述
- E.2 Naming conventions
- E.3 Portability
- E.4 Include files
- E.5 Semantic constraints
- E.6 Data types
- E.7 Argument passing modes
- E.8 Context tasks and functions
- E.9 Include files
- E.10 Arrays
- E.11 Open arrays
- E.11.1 Actual ranges
- E.11.2 Array querying functions
- E.11.3 Access functions
- E.11.4 Access to the actual representation
- E.11.5 Access to elements via canonical representation
- E.11.6 Access to scalar elements (bit and logic)
- E.11.7 Access to array elements of other types
- E.11.8 Example 4— two-dimensional open array
- E.11.9 Example 5 — open array
- E.11.10 Example 6 — access to packed arrays
- E.11.11 Example 7 — binary compatible calls of exported functions
- 附录F 包含文件
- 附录G 包含外部语言代码
- 附录H 并发断言的形式语义
- 附录I svvpiuser.h
- 附录J 术语表
- 附录K 参考书目
- 其他
20.2 定义覆盖模型:covergroup
The covergroup construct encapsulates the specification of a coverage model. Each covergroup specification can include the following components:
- A clocking event that synchronizes the sampling of coverage points
- A set of coverage points
- Cross coverage between coverage points
- Optional formal arguments
- Coverage options
covergroup_declaration ::= // from Annex A.2.11 covergroup covergroup_identifier[([tf_port_list])][coverage_event]; {coverage_spec_or_option;} endgroup [: covergroup_identifier] coverage_spec_or_option ::= {attribute_instance} coverage_spec | {attribute_instance} coverage_option; coverage_option ::= option.member_identifier = expression | type_option.member_identifier = expression coverage_spec ::= cover_point | cover_cross coverage_event ::= clocking_event | @@(block_event_expression) block_event_expression :: = block_event_expression or block_event_expression | begin hierarchical_btf_identifier | end hierarchical_btf_identifier hierarchical_btf_identifier :: = hierarchical_tf_identifier | hierarchical_block_identifier | hierarchical_identifier [class_scope] method_identifier variable_decl_assignment ::= // from Annex A.2.4 ... | [covergroup_variable_identifier] = new[(list_of_arguments)] // 16 16. It shall be legal to omit the covergroup_variable_identifer from a covergroup instantiation only if this implicit instantiation is within a class that has no other instantiation of the covergroup.
Syntax 20-1—Covergroup syntax (excerpt from Annex A)
The identifier associated with the covergroup declaration defines the name of the coverage model. Using this name, an arbitrary number of coverage model instances can be created. For example:
covergroup cg; ... endgroup cg cg_inst = new;
The above example defines a covergroup named cg. An instance of cg is declared as cg_inst and created using the new operator.
A covergroup can specify an optional list of arguments. When the covergroup specifies a list of formal arguments, its instances must provide to the new operator all the actual arguments that are not defaulted. Actual arguments are evaluated when the new operator is executed. A ref argument allows a different variable to be sampled by each instance of a covergroup. Input arguments will not track value of their arguments; they will use the value passed to the new operator.
If a clocking event is specified, it defines the event at which coverage points are sampled. If the clocking event is omitted, users must procedurally trigger the coverage sampling. This is done via the built-in sample() method (see Section 20.7). Optionally, the strobe option can be used to modify the sampling behavior. When the strobe option is not set (the default), a coverage point is sampled the instant the clocking event takes place, as if the process triggering the event were to call the built-in sample() method. If the clocking event occurs multiple times in a time step, the coverage point will also be sampled multiple times. The strobe option (see Section 20.6.1) can be used to specify that coverage points are sampled in the postponed region, thereby filtering multiple clocking events so that only one sample per time slot is taken.
As an alternative to a clocking event, a coverage group accepts a block event expression to indicate that the coverage sample is to be triggered by the start or the end of execution of a given named block, task, function, or class method. Block event expressions that specify the begin keyword followed by a hierarchical identifier denoting a named block, task, function, or class method shall be triggered immediately before the corresponding block, task, function, or method begins executing its first statement. Block event expressions that specify the end keyword followed by a hierarchical identifier denoting a named block, task, function, or class method shall be triggered immediately after the corresponding block, task, function, or method executes its last statement.Block event expressions that specify the end of execution shall not be triggered if the block, task, function, or method is disabled.
A covergroup can contain one or more coverage points. A coverage point can be a variable or an expression. Each coverage point includes a set of bins associated with its sampled values or its value-transitions. The bins can be explicitly defined by the user or automatically created by the tool. Coverage points are discussed in detail in Section 20.4.
enum { red, green, blue } color; covergroup g1 @(posedge clk); c: coverpoint color; endgroup
The above example defines coverage group g1 with a single coverage point associated with variable color. The value of the variable color is sampled at the indicated clocking event: the positive edge of signal clk. Since the coverage point does not explicitly define any bins, the tool automatically creates 3 bins, one for each possible value of the enumerated type. Automatic bins are described in Section 20.4.2.
A coverage group can also specify cross coverage between two or more coverage points or variables. Any combination of more than two variables or previously declared coverage points is allowed. For example:
enum { red, green, blue } color; bit [3:0] pixel_adr, pixel_offset, pixel_hue; covergroup g2 @(posedge clk); Hue: coverpoint pixel_hue; Offset: coverpoint pixel_offset; AxC: cross color, pixel_adr; // cross 2 variables (implicitly declared // coverpoints) all: cross color, Hue, Offset; // cross 1 variable and 2 coverpoints endgroup
The example above creates coverage group g2 that includes 2 coverage points and two cross coverage items. Explicit coverage points labeled Offset and Hue are defined for variables pixel_offset and pixel_hue. SystemVerilog implicitly declares coverage points for variables color and pixel_adr in order to track their cross coverage. Implicitly declared cover points are described in Section 20.5.
A coverage group can also specify one or more options to control and regulate how coverage data is structured and collected. Coverage options can be specified for the coverage group as a whole, or for specific items within the coverage group, that is, any of its coverage points or crosses. In general, a coverage option specified at the covergroup level applies to all of its items unless overridden by them. Coverage options are described in Section 20.6.
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