- 第一章 SystemVerilog导论
- 第二章 文本值
- 第三章 数据类型
- 第四章 数组
- 第五章 数据声明
- 第六章 属性
- 第七章 操作符与表达式
- 第八章 过程语句和控制流
- 第九章 进程
- 第十章 任务与函数
- 第十一章 类
- 第十二章 随机约束
- 第十三章 进程间的同步与通信
- 第十四章 调度语义
- 第十五章 时钟控制块
- 第十六章 程序块
- 第十七章 断言
- 第十八章 层次
- 第十九章 接口
- 第二十章 覆盖
- 第二十一章 参数
- 第二十二章 配置库
- 第二十三章 系统任务与系统函数
- 23.1 简介(一般信息)
- 23.2 确立时的typeof函数
- 23.3 typename函数
- 23.4 表达式尺寸系统函数
- 23.5 范围系统函数
- 23.6 Shortreal转换
- 23.7 数组查询系统函数
- 23.8 断言严重性系统任务
- 23.9 断言控制系统任务
- 23.10 断言系统函数
- 23.11 随机数系统函数
- 23.12 程序控制
- 23.13 覆盖系统函数
- 23.14 对Verilog-2001系统任务的增强
- 23.15 $readmemb与$readmemh
- 23.16 $writememb and $writememh
- 23.17 File format considerations for multi-dimensional unpacked arrays
- 23.18 System task arguments for multi-dimensional unpacked arrays
- 第二十四章 VCD数据
- 第二十五章 编译器指令
- 第二十六章 考虑从SystemVerilog中删除的功能
- 第二十七章 直接编程接口(DPI)
- 27.1 概述
- 27.2 Two layers of the DPI
- 27.3 Global name space of imported and exported functions
- 27.4 导入的任务和函数
- 27.5 Calling imported functions
- 27.6 Exported functions
- 27.7 Exported tasks
- 27.8 Disabling DPI tasks and functions
- 第二十八章 SystemVerilog断言API
- 第二十九章 SystemVerilog覆盖API
- 29.1 需求
- 29.2 SystemVerilog real-time coverage access
- 29.3 FSM recognition
- 29.3.1 Specifying the signal that holds the current state
- 29.3.2 Specifying the part-select that holds the current state
- 29.3.3 Specifying the concatenation that holds the current state
- 29.3.4 Specifying the signal that holds the next state
- 29.3.5 Specifying the current and next state signals in the same declaration
- 29.3.6 Specifying the possible states of the FSM
- 29.3.7 Pragmas in one-line comments
- 29.3.8 Example
- 29.4 VPI coverage extensions
- 第三十章 SystemVerilog数据读API
- 30.1 简介(一般信息)
- 30.2 需求
- 30.3 Extensions to VPI enumerations
- 30.4 VPI object type additions
- 30.5 Object model diagrams
- 30.6 Usage extensions to VPI routines
- 30.7 VPI routines added in SystemVerilog
- 30.8 Reading data
- 30.9 Optionally unloading the data
- 30.10 Reading data from multiple databases and/or different read library providers
- 30.11 VPI routines extended in SystemVerilog
- 30.12 VPI routines added in SystemVerilog
- 30.12.1 VPI reader routines
- 第三十一章 SystemVerilog VPI Object Model
- 31.1 简介(一般信息)
- 31.2 Instance
- 31.3 Interface
- 31.4 Program
- 31.5 Module (supersedes IEEE 1364-2001 26.6.1)
- 31.6 Modport
- 31.7 Interface tf decl
- 31.8 Ports (supersedes IEEE 1364-2001 26.6.5)
- 31.9 Ref Obj
- 31.9.1 Examples
- 31.10 Variables (supersedes IEEE 1364-2001 section 26.6.8)
- 31.11 Var Select (supersedes IEEE 1364-2001 26.6.8)
- 31.12 Typespec
- 31.13 Variable Drivers and Loads (supersedes IEEE 1364-2001 26.6.23)
- 31.14 Instance Arrays (supersedes IEEE 1364-2001 26.6.2)
- 31.15 Scope (supersedes IEEE 1364-2001 26.6.3)
- 31.16 IO Declaration (supersedes IEEE 1364-2001 26.6.4)
- 31.17 Clocking Block
- 31.18 Class Object Definition
- 31.19 Constraint, constraint ordering, distribution,
- 31.20 Constraint expression
- 31.21 Class Variables
- 31.22 Structure/Union
- 31.23 Named Events (supersedes IEEE 1364-2001 26.6.11)
- 31.24 Task, Function Declaration (supersedes IEEE 1364-2001 26.6.18)
- 31.25 Alias Statement
- 31.25.1 Examples
- 31.26 Frames (supersedes IEEE 1364-2001 26.6.20)
- 31.27 Threads
- 31.28 tf call (supersedes IEEE 1364-2001 26.6.19)
- 31.29 Module path, path term (supersedes IEEE 1364-2001 26.6.15)
- 31.30 Concurrent assertions
- 31.31 Property Decl
- 31.32 Property Specification
- 31.33 Multiclock Sequence Expression
- 31.34 Sequence Declaration
- 31.35 Sequence Expression
- 31.36 Attribute (supersedes IEEE 1364-2001 26.6.42)
- 31.37 Atomic Statement (supersedes IEEE 1364-2001 26.6.27)
- 31.38 If, if else, return, case, do while (supersedes IEEE 1364-2001 26.6.35, 26.6.36)
- 31.39 waits, disables, expect, foreach (supersedes IEEE 1364 26.6.38)
- 31.40 Simple expressions (supersedes IEEE 1364-2001 26.6.25)
- 31.41 Expressions (supersedes IEEE 1364-2001 26.6.26)
- 31.42 Event control (supersedes IEEE 1364-2001 26.6.30)
- 31.43 Event stmt (supersedes IEEE 1364-2001 26.6.27)
- 31.44 Process (supersedes IEEE 1364-2001 26.6.27)
- 31.45 Assignment (supersedes IEEE 1364-2001 26.6.28)
- 附录A 形式语法
- A.1 源文本
- A.2 声明
- A.3 Primitive instances
- A.4 Module, interface and generated instantiation
- A.5 UDP declaration and instantiation
- A.6 Behavioral statements
- A.6.1 Continuous assignment and net alias statements
- A.6.2 Procedural blocks and assignments
- A.6.3 Parallel and sequential blocks
- A.6.4 Statements
- A.6.5 Timing control statements
- A.6.6 Conditional statements
- A.6.7 Case statements
- A.6.8 Looping statements
- A.6.9 Subroutine call statements
- A.6.10 Assertion statements
- A.6.11 Clocking block
- A.6.12 Randsequence
- A.7 Specify section
- A.8 Expressions
- A.9 General
- A.10 Footnotes (normative)
- 附录B 关键字
- 附录C 标准包
- 附录D 链表
- 附录E DPI C-layer
- E.1 概述
- E.2 Naming conventions
- E.3 Portability
- E.4 Include files
- E.5 Semantic constraints
- E.6 Data types
- E.7 Argument passing modes
- E.8 Context tasks and functions
- E.9 Include files
- E.10 Arrays
- E.11 Open arrays
- E.11.1 Actual ranges
- E.11.2 Array querying functions
- E.11.3 Access functions
- E.11.4 Access to the actual representation
- E.11.5 Access to elements via canonical representation
- E.11.6 Access to scalar elements (bit and logic)
- E.11.7 Access to array elements of other types
- E.11.8 Example 4— two-dimensional open array
- E.11.9 Example 5 — open array
- E.11.10 Example 6 — access to packed arrays
- E.11.11 Example 7 — binary compatible calls of exported functions
- 附录F 包含文件
- 附录G 包含外部语言代码
- 附录H 并发断言的形式语义
- 附录I svvpiuser.h
- 附录J 术语表
- 附录K 参考书目
- 其他
20.5 Defining cross coverage
A coverage group can specify cross coverage between two or more coverage points or variables. Cross coverage is specified using the cross construct. When a variable V is part of a cross coverage, SystemVerilog implicitly creates a coverage point for the variable, as if it had been created by the statement coverpoint V;. Thus, a cross involves only coverage points. Expressions cannot be used directly in a cross; a coverage point must be explicitly defined first.
The syntax for specifying cross coverage is given below.
cover_cross ::= // from Annex A.2.11 [cover_point_identifer :] cross list_of_coverpoints[iff(expression)] select_bins_or_empty list_of_coverpoints ::= cross_item , cross_item {, cross_item } cross_item ::= cover_point_identifier | variable_identifier select_bins_or_empty ::= {{bins_selections_or_option;}} | ; bins_selection_or_option ::= {attribute_instance} coverage_option | {attribute_instance} bins_selection bins_selection ::= bins_keyword bin_identifier=select_expression[iff(expression)] select_expression ::= select_condition | !select_condition | select_expression && select_expression | select_expression || select_expression | (select_expression) select_condition ::= binsof(bins_expression)[intersect{open_range_list}] bins_expression ::= variable_identifier | cover_point_identifier[.bins_identifier] open_range_list ::= open_value_range {, open_value_range} open_value_range ::= value_range
Syntax 20-4—Cross coverage syntax (excerpt from Annex A)
The label for a cross declaration provides an optional name. The label also creates a hierarchical scope for the bins defined within the cross.
The expression within the optional iff provides a conditional guard for the cross coverage. If at any sample point, the condition evaluates to false, the cross coverage is ignored. The expression within the optional iff construct at the end of a cross bin definition provides a per-bin guard condition. If the expression is false, the cross bin is ignored.
Cross coverage of a set of N coverage points is defined as the coverage of all combinations of all bins associated with the N coverage points, that is, the Cartesian product of the N sets of coverage-point bins. For example:
bit [3:0] a, b; covergroup cov @(posedge clk); aXb : cross a, b; endgroup
The coverage group cov in the example above specifies the cross coverage of two 4-bit variables, a and b. SystemVerilog implicitly creates a coverage point for each variable. Each coverage point has 16 bins, namely auto[0]...auto[15]. The cross of a and b (labeled aXb), therefore, has 256 cross products, and each cross product is a bin of aXb.
Cross coverage between expressions previously defined as coverage points is also allowed. For example:
bit [3:0] a, b, c; covergroup cov2 @(posedge clk); BC: coverpoint b+c; aXb : cross a, BC; endgroup
The coverage group cov2 has the same number of cross products as the previous example, but in this case, one of the coverage points is the expression b+c, which is labeled BC.
bit [31:0] a_var; bit [3:0] b_var; covergroup cov3 @(posedge clk); A: coverpoint a_var { bins yy[] = { [0:9] }; } CC: cross b_var, A; endgroup
The coverage group cov3 crosses variable b_var with coverage point A (labeled CC). Variable b_var automatically creates 16 bins (auto[0]...auto[15]). Coverage point A explicitly creates 10 bins yy[0]...yy[9]. The cross of two coverage points creates 16 * 10 = 160 cross product bins, namely the pairs shown below:
<auto[0], yy[0]> <auto[0], yy[1]> ... <auto[0], yy[9]> <auto[1], yy[0]> ... <auto[15], yy[9]>
Cross coverage is allowed only between coverage points defined within the same coverage group. Coverage points defined in a coverage group other than the one enclosing the cross cannot participate in a cross. Attempts to cross items from different coverage groups shall result in a compiler error.
In addition to specifying the coverage points that are crossed, SystemVerilog includes a powerful set of operators that allow defining cross coverage bins. Cross coverage bins can be specified in order to group together a set of cross products. A cross-coverage bin associates a name and a count with a set of cross products. The count of the bin is incremented every time any of the cross products match, i.e., every coverage point in the cross matches its corresponding bin in the cross product.
User-defined bins for cross coverage are defined using bins select-expressions. The syntax for defining these bin selection expressions is given in Syntax 20-4.
The binsof construct yields the bins of its expression, which can be either a coverage point (explicitly defined or implicitly defined for a single variable) or a coverage-point bin. The resulting bins can be further selected by including (or excluding) only the bins whose associated values intersect a desired set of values. The desired set of values can be specified using a comma-separated list of open_value_range as shown in Syntax 20-4. For example, the following select expression:
binsof( x ) intersect { y }
denotes the bins of coverage point x whose values intersect the range given by y. Its negated form:
! binsof( x ) intersect { y }
denotes the bins of coverage point x whose values do not intersect the range given by y.
The open_value_range syntax can specify a single value, a range of values, or an open range, which denotes the following:
[ $ : value ] => The set of values less than or equal to value [ value : $ ] => The set of values greater or equal to value
The bins selected can be combined with other selected bins using the logical operators && and || .
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