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20.5 Defining cross coverage

发布于 2020-09-09 22:55:56 字数 5981 浏览 984 评论 0 收藏 0

A coverage group can specify cross coverage between two or more coverage points or variables. Cross coverage is specified using the cross construct. When a variable V is part of a cross coverage, SystemVerilog implicitly creates a coverage point for the variable, as if it had been created by the statement coverpoint V;. Thus, a cross involves only coverage points. Expressions cannot be used directly in a cross; a coverage point must be explicitly defined first.

The syntax for specifying cross coverage is given below.

cover_cross ::=         // from Annex A.2.11
    [cover_point_identifer :] cross list_of_coverpoints[iff(expression)] select_bins_or_empty

list_of_coverpoints ::= cross_item , cross_item {, cross_item }

cross_item ::=
    cover_point_identifier
  | variable_identifier

select_bins_or_empty ::=
    {{bins_selections_or_option;}}
  | ;

bins_selection_or_option ::=
    {attribute_instance} coverage_option
  | {attribute_instance} bins_selection

bins_selection ::= bins_keyword bin_identifier=select_expression[iff(expression)]

select_expression ::=
    select_condition
  | !select_condition
  | select_expression && select_expression
  | select_expression || select_expression
  | (select_expression)

select_condition ::= binsof(bins_expression)[intersect{open_range_list}]

bins_expression ::=
    variable_identifier
  | cover_point_identifier[.bins_identifier]

open_range_list ::= open_value_range {, open_value_range}

open_value_range ::= value_range

Syntax 20-4—Cross coverage syntax (excerpt from Annex A)

The label for a cross declaration provides an optional name. The label also creates a hierarchical scope for the bins defined within the cross.

The expression within the optional iff provides a conditional guard for the cross coverage. If at any sample point, the condition evaluates to false, the cross coverage is ignored. The expression within the optional iff construct at the end of a cross bin definition provides a per-bin guard condition. If the expression is false, the cross bin is ignored.

Cross coverage of a set of N coverage points is defined as the coverage of all combinations of all bins associated with the N coverage points, that is, the Cartesian product of the N sets of coverage-point bins. For example:

bit [3:0] a, b;
covergroup cov @(posedge clk);
    aXb : cross a, b;
endgroup

The coverage group cov in the example above specifies the cross coverage of two 4-bit variables, a and b. SystemVerilog implicitly creates a coverage point for each variable. Each coverage point has 16 bins, namely auto[0]...auto[15]. The cross of a and b (labeled aXb), therefore, has 256 cross products, and each cross product is a bin of aXb.

Cross coverage between expressions previously defined as coverage points is also allowed. For example:

bit [3:0] a, b, c;

covergroup cov2 @(posedge clk);
    BC: coverpoint b+c;
    aXb : cross a, BC;
endgroup

The coverage group cov2 has the same number of cross products as the previous example, but in this case, one of the coverage points is the expression b+c, which is labeled BC.

bit [31:0] a_var;
bit [3:0] b_var;

covergroup cov3 @(posedge clk);
    A: coverpoint a_var { bins yy[] = { [0:9] }; }
    CC: cross b_var, A;
endgroup

The coverage group cov3 crosses variable b_var with coverage point A (labeled CC). Variable b_var automatically creates 16 bins (auto[0]...auto[15]). Coverage point A explicitly creates 10 bins yy[0]...yy[9]. The cross of two coverage points creates 16 * 10 = 160 cross product bins, namely the pairs shown below:

<auto[0], yy[0]>
<auto[0], yy[1]>
...
<auto[0], yy[9]>
<auto[1], yy[0]>
...
<auto[15], yy[9]>

Cross coverage is allowed only between coverage points defined within the same coverage group. Coverage points defined in a coverage group other than the one enclosing the cross cannot participate in a cross. Attempts to cross items from different coverage groups shall result in a compiler error.

In addition to specifying the coverage points that are crossed, SystemVerilog includes a powerful set of operators that allow defining cross coverage bins. Cross coverage bins can be specified in order to group together a set of cross products. A cross-coverage bin associates a name and a count with a set of cross products. The count of the bin is incremented every time any of the cross products match, i.e., every coverage point in the cross matches its corresponding bin in the cross product.

User-defined bins for cross coverage are defined using bins select-expressions. The syntax for defining these bin selection expressions is given in Syntax 20-4.

The binsof construct yields the bins of its expression, which can be either a coverage point (explicitly defined or implicitly defined for a single variable) or a coverage-point bin. The resulting bins can be further selected by including (or excluding) only the bins whose associated values intersect a desired set of values. The desired set of values can be specified using a comma-separated list of open_value_range as shown in Syntax 20-4. For example, the following select expression:

binsof( x ) intersect { y }

denotes the bins of coverage point x whose values intersect the range given by y. Its negated form:

! binsof( x ) intersect { y }

denotes the bins of coverage point x whose values do not intersect the range given by y.

The open_value_range syntax can specify a single value, a range of values, or an open range, which denotes the following:

[ $ : value ] => The set of values less than or equal to value
[ value : $ ] => The set of values greater or equal to value

The bins selected can be combined with other selected bins using the logical operators && and || .

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