Question

通过使用编译单元，SystemVerilog支持分离的编译。SystemVerilog提供了下列的术语和定义：

• 编译单元：a collection of one or more SystemVerilog source files compiled together
• 编译单元作用域：a scope that is local to the compilation unit. It contains all declarations that lie outside of any other scope
• $unit：用来显式地访问编译单元作用域中的标识符的名字

The exact mechanism for defining which files constitute a compilation unit is tool specific. Tools shall provide a mechanism to specify the files that make up a compilation unit. Two extreme cases are:

1. All files make a single compilation unit (in which case the declarations in the compilation-unit scope are accessible anywhere within the design)
2. Each file is a separate compilation unit (in which case the declarations in each compilation-unit scope are accessible only within its corresponding file)

The contents of files included using one or more ‘include directives become part of the compilation unit of the file they are included within.

If there is a declaration that is incomplete at the end of a file, then the compilation unit including that file will extend through each successive file until there are no incomplete declarations at the end of the group of files.

The default is that each file is a separate compilation unit.

A tool must also provide a mechanism (such as a command line switch) that specifies that all of the files compiled together are a single compilation unit.

There are other possible mappings of files to compilation units and the mechanism for defining them are tool specific and may not be portable.

The compilation-unit scope can contain any item that can be defined within a package. These items are in the compilation-unit scope name space.

The following items are visible in all compilation units: modules, macromodules, primitives, programs, interfaces, and packages. Items defined in the compilation-unit scope cannot be accessed by name from outside the compilation unit. Access to the items in a compilation-unit scope can be accessed using the PLI, which must provide an iterator to traverse all the compilation units.

In Verilog, compiler directives once seen by a tool apply to all forthcoming source text. This behavior shall be supported within a separately compiled unit; however, compiler directives from one separately compiled unit shall not affect other compilation units. This may result in a difference of behavior between compiling the units separately or as a single compilation unit containing the entire source.

When an identifier is referenced within a scope, SystemVerilog follows the Verilog name search rules:

• First, the nested scope is searched (1364-2001 12.6) (including nested module declarations), including any identifiers made available through package import declarations
• Next, the compilation-unit scope is searched (including any identifiers made available through package import declarations
• Finally, the instance hierarchy is searched (1364-2001 12.5)

$unit is the name of the scope that encompasses a compilation unit. Its purpose is to allow the unambiguous reference to declarations at the outermost level of a compilation unit (i.e., those in the compilation-unit scope).This is done via the same scope resolution operator used to access package items.

For example:

bit b;

task foo;
    int b;
    b = 5 + $unit::b; // $unit::b is the one outside
endtask

The compilation-unit scope allows users to easily share declarations (e.g., types) across the unit of compilation, but without having to declare a package from which the declarations are subsequently imported. Thus, the compilation-unit scope is similar to an implicitly defined anonymous package. Because it has no name, the compilation-unit scope cannot be used with an import statement, and the identifiers declared within the scope are not accessible via hierarchical references. Within a particular compilation unit, however, the special name $unit can be used to explicitly access the declarations of its compilation-unit scope.