Question

The formal syntax of SystemVerilog is described using Backus-Naur Form (BNF). The conventions used are:

• Keywords and punctuation are in bold text.
• Syntactic categories are named in non-bold text.
• A vertical bar (|) separates alternatives.
• Square brackets ([]) enclose optional items.
• Braces ({}) enclose items which can be repeated zero or more times.

The full syntax and semantics of Verilog and SystemVerilog are not described solely using BNF. The normative text description contained within the chapters of the IEEE 1364-2001 Verilog standard and this SystemVerilog document provide additional details on the syntax and semantics described in this BNF.

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主题	描述
A.1 源文本
A.2 声明
A.3 Primitive instances
A.4 Module, interface and generated instantiation
A.5 UDP declaration and instantiation
A.6 Behavioral statements
A.7 Specify section
A.8 Expressions
A.9 General
A.10 Footnotes (normative)	Embedded spaces are illegal. A simple_identifier, c_identifier, and arrayed_reference shall start with an alpha or underscore ( _ ) character, shall have at least one character, and shall not have any spaces. The $ character in a system_tf_identifier shall not be followed by white_space. A system_tf_identifier shall not be escaped. End of file. The unsigned number or fixed point number in time_literal shall not be followed by a white_space. implicit_class_handle shall only appear within the scope of a class_declaration or out-of-block method declaration. In any one declaration, only one of protected or local is allowed, only one of rand or... more

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