Question

The modport construct can also be used to specify the direction of clocking blocks declared within an interface. As with other modport declarations, the directions of the clocking block are those seen from the module in which the interface becomes a port. The syntax for this is shown below.

modport_declaration ::= modport modport_item {, modport_item};  // from Annex A.2.9

modport_item ::= modport_identifier(modport_ports_declaration {, modport_ports_declaration})

modport_ports_declaration ::=
    {attribute_instance} modport_simple_ports_declaration
  | {attribute_instance} modport_hierarchical_ports_declaration
  | {attribute_instance} modport_tf_ports_declaration
  | {attribute_instance} modport_clocking_declaration

modport_clocking_declaration ::= clocking clocking_identifier

Syntax 19-2—modport clocking declaration syntax (excerpt from Annex A)

All of the clocking blocks used in a modport declaration shall be declared by the same interface as is the modport itself. Like all modport declarations, the direction of the clocking signals are those seen from the module in which the interface becomes a port. The example below shows how modports can be used to create both synchronous as well as asynchronous ports. When used in conjunction with virtual interfaces (see Section 19.8.2), these constructs facilitate the creation of abstract synchronous models.

interface A_Bus( input bit clk );
    wire req, gnt;
    wire [7:0] addr, data;
    clocking sb @(posedge clk);
        input gnt;
        output req, addr;
        inout data;
        property p1; req ##[1:3] gnt; endproperty
    endclocking

    modport DUT (input clk, req, addr, // Device under test modport
                 output gnt,
                 inout data );

    modport STB (clocking sb); // synchronous testbench modport
    modport TB (input gnt, // asynchronous testbench modport
                output req, addr,
                inout data );
endinterface

The above interface A_Bus can then be instantiated as shown below:

module dev1(A_Bus.DUT b); // Some device: Part of the design
    ...
endmodule

module dev2(A_Bus.DUT b); // Some device: Part of the design
    ...
endmodule

module top;
    bit clk;
    A_Bus b1( clk );
    A_Bus b2( clk );
    dev1 d1( b1 );
    dev2 d2( b2 );
    T tb( b1, b2 );
endmodule

program T (A_Bus.STB b1, A_Bus.STB b2 ); // Testbench: 2 synchronous ports
    assert property (b1.p1); // assert property from within program
    initial begin
        b1.sb.req <= 1;
        wait( b1.sb.gnt == 1 );
        ...
        b1.sb.req <= 0;
        b2.sb.req <= 1;
        wait( b2.sb.gnt == 1 );
        ...
        b2.sb.req <= 0;
    end
endprogram

The example above shows the program block using the synchronous interface designated by the clockingmodport of interface ports b1 and b2. In addition to the procedural drives and samples of the clocking block signals, the program asserts the property p1 of one of its interfaces b1.