Question

module_declaration ::=         // 引用自附录A.1.3
    module_nonansi_header [timeunits_declaration] {module_item}
        endmodule [: module_identifier]
  | module_ansi_header [timeunits_declaration] {non_port_module_item}
        endmodule [: module_identifier]
  | {attribute_instance} module_keyword [lifetime] module_identifier(.*);
        [timeunits_declaration] {module_item} endmodule [: module_identifier]
  | extern module_nonansi_header
  | extern module_ansi_header

module_nonansi_header ::=
    {attribute_instance} module_keyword [lifetime] module_identifier [parameter_port_list]
        list_of_ports;

module_ansi_header ::=
    {attribute_instance} module_keyword [lifetime] module_identifier [parameter_port_list]
        [list_of_port_declarations];

module_keyword ::= module | macromodule

timeunits_declaration ::=
    timeunit time_literal;
  | timeprecision time_literal;
  | timeunit time_literal;
    timeprecision time_literal;
  | timeprecision time_literal;
    timeunit time_literal;

Syntax 18-3—Module declaration syntax (excerpt from Annex A)

In Verilog, a module must be declared apart from other modules, and can only be instantiated within another module. A module declaration can appear after it is instantiated in the source text.

SystemVerilog adds the capability to nest module declarations.

module m1(...); ... endmodule
module m2(...); ... endmodule
module m3(...);
    m1 i1(...); // instantiates the local m1 declared below
    m2 i4(...); // instantiates m2 - no local declaration
    module m1(...); ... endmodule // nested module declaration,
    // m1 module name is in m3’s name space
endmodule