Question

This example shows a simple bus implemented without interfaces. Note that the logic type can replace wire and reg if no resolution of multiple drivers is needed.

module memMod( input    bit req,
                        bit clk,
                        bit start,
                        logic [1:0] mode,
                        logic [7:0] addr,
               inout    wire [7:0] data,
               output   bit gnt,
                        bit rdy );
    logic avail;
    ...
endmodule

module cpuMod(
    input   bit clk,
            bit gnt,
            bit rdy,
    inout   wire [7:0] data,
    output  bit req,
            bit start,
            logic [7:0] addr,
            logic [1:0] mode );
    ...
endmodule

module top;
    logic req, gnt, start, rdy; // req is logic not bit here
    logic clk = 0;
    logic [1:0] mode;
    logic [7:0] addr;
    wire [7:0] data;

    memMod mem(req, clk, start, mode, addr, data, gnt, rdy);

    cpuMod cpu(clk, gnt, rdy, data, req, start, addr, mode);
endmodule