Question

To support separate compilation, extern declarations of a module can be used to declare the ports on a module without defining the module itself. An extern module declaration consists of the keyword extern followed by the module name and the list of ports for the module. Both list of ports syntax (possibly with parameters), and original Verilog style port declarations can be used. Note that the potential existence of defparams precludes the checking of the port connection information prior to elaboration time even for list of ports style declarations.

The following example demonstrates the usage of extern module declarations.

extern module m (a,b,c,d);
extern module a #(parameter size= 8, parameter type TP = logic [7:0])
                 (input [size:0] a, output TP b);
module top ();
    wire [8:0] a;
    logic [7:0] b;
    m m (.*);
    a a (.*);
endmodule

Modules m and a are then assumed to be instantiated as:

module top ();
    m m (a,b,c,d);
    a a (a,b);
endmodule

If an extern declaration exists for a module, it is possible to use .* as the ports of the module. This usage shall be equivalent to placing the ports (and possibly parameters) of the extern declaration on the module.

For example,

extern module m (a,b,c,d);
extern module a #(parameter size = 8, parameter type TP = logic [7:0])
                 (input [size:0] a, output TP b);
module m (.*);
    input a,b,c;
    output d;
endmodule

module a (.*);
    ...
endmodule

is equivalent to writing:

module m (a,b,c,d);
    input a,b,c;
    output d;
endmodule

module a #(parameter size = 8, parameter type TP = logic [7:0])
          (input [size:0] a, output TP b);
    ...
endmodule

Extern module declarations can appear at any level of the instantiation hierarchy, but are visible only within the level of hierarchy in which they are declared. It shall be an error for the module definition to not exactly match the extern module declaration.